Matches 1 - 45 out of 45

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US20130124930 CONTROLLING IPSEC OFFLOAD ENABLEMENT DURING HARDWARE FAILURES  
Provided are techniques for receiving a packet transmitted in conjunction with a security association associated with Internet Protocol Security (IPSec); determining, based upon the security...
US20150012783 Techniques for Radio Link Problem and Recovery Detection in a Wireless Communication System  
A technique for radio link detection in a wireless communication system includes estimating a first error rate of an indicator channel. In this case, the indicator channel includes an indication...
US20130061099 EFFICIENT ERROR HANDLING ON A LINK USING ARQ AND MULTIPLE NACKS ASSOCIATED WITH MULTIPLE ERROR THRESHOLDS  
The present invention describes how to handle errors occurring during communication in a frame-based communication system that uses a communication protocol having a first error handling mechanism...
US20090271668 Bus Failure Management Method and System  
A method, apparatus and program product improve computer reliability by, in part, identifying a plurality of error occurrences from Error Correction Codes. It may then be determined if the...
US20110065443 BLOCK ENCODING WITH A VARIABLE RATE BLOCK CODE  
A control channel encoder includes a determiner to determine a current value of K for encoding control signals of a length M, wherein K is a function of a code rate for a data channel. A table...
US20090183038 METHOD FOR IMPROVING THE INTEGRITY OF COMMUNICATION MEANS  
Embodiments of the invention enable the integrity of data processed by a switch to be guaranteed better than 10−9 undetected erroneous frames per flight hour. To do this, rules for disabling ports...
US20100033861 ERROR BURST DETECTION AND AMELIORATION  
A method according to one embodiment includes monitoring a data transfer operation for detecting temporary errors; determining whether art error burst has occurred based on the monitoring; if an...
US20120216084 SERDES POWER THROTTLING AS A FUNCTION OF DETECTED ERROR RATE  
A system involves a first SerDes link from a first integrated circuit (IC) to a second IC and a second link from the second IC to the first IC. Power consumption settings in circuitry of the first...
US20130339811 BITLINE DELETION  
Embodiments relate to a method for bitline deletion include, based on detecting a high bitline error rate condition in the cache at a selected bitline address, wherein the high bitline error rate...
US20080184081 DATA COMMUNICATION APPARATUS, METHOD, AND PROGRAM  
A data communication apparatus determines whether the error type is a burst error or not based on an error occurrence state of the data received from a data transmitting apparatus and transmits...
US20100083061 Method to Manage Path Failure Thresholds  
A failure threshold host command that provides a host with the capability to tune a storage controller path failure threshold based on the host application performance requirements. The failure...
US20130139009 SCHEDULING FOR ENHANCING COMMUNICATION PERFORMANCE  
Technologies are generally described for enhancing communication performance. In some examples, a scheduling system may include an error detection unit configured to detect existence of an error...
US20120272105 HOME NETWORK ENCRYPTION TECHNIQUES  
A premises based multimedia communication system includes a source device that produces multimedia content, a rendering device that presents the multimedia content, and a premises communication...
US20090024883 INTER-ASIC DATA TRANSPORT USING LINK CONTROL BLOCK MANAGER  
An apparatus comprising a SerDes circuit and a link control block (LCB). The SerDes circuit is a first end of a SerDes circuit pair of a SerDes lane. A SerDes lane includes the SerDes circuit pair...
US20090144591 DETERMINING BIT ERROR RATE USING SINGLE DATA BURST  
A communication system comprises a transceiver capable of receiving a data burst as part of a paging block. The system also comprises processing logic capable of comparing at least part of the...
US20070124627 Communication processing device, home electric device, and home network system  
A transmission rate negotiation between multi-rate home electric device 100 and communication processing device 200 is completed by sending and receiving a line connection request containing...
US20090228747 Test system for conducting Parallel bit test  
Provided is a test system conducting a parallel bit test. The test system, conducting a parallel bit test on a plurality of memory modules mounted on a socket, comprises a plurality of counters...
US20130047044 OPTIMAL PROGRAMMING LEVELS FOR LDPC  
The subject disclosure describes a method for reducing a sector error rate in a flash memory device, the method comprising, identifying a first program verify level having a first value, selecting...
US20150095727 RATE ADAPTATION METHOD USING BIT ERROR RATE FOR MULTIMEDIA SERVICE AND APPARATUS THEREFOR  
Rate adaptation is carried out using bit error rate (BER) to enable effective multimedia transmission. The BER can be estimated using signal strength in a MAC layer and modulation information...
US20090063911 DIGITAL BROADCAST RECEIVER  
In digital broadcast receiver (100), when a bit error rate (BER) is larger than a threshold in BER determining part (109), power is supplied to tuner (103) and tuner (104) for diversity reception....
US20080022022 INFORMATION TRANSMISSION DEVICE AND INFORMATION TRANSMISSION METHOD  
An information transmission device that is included in components and carries out communication between the components in an information processing device including a control monitoring unit that...
US20100332923 SYSTEM AND METHOD RESPONSIVE TO A RATE OF CHANGE OF A PERFORMANCE PARAMETER OF A MEMORY  
Systems and methods are disclosed that are responsive to a rate of change of a performance parameter of a memory. In a particular embodiment, a rate of change of a performance parameter of a...
US20090282300 Partition Transparent Memory Error Handling in a Logically Partitioned Computer System With Mirrored Memory  
A method and apparatus for transparently handling recurring correctable errors and uncorrectable errors in a mirrored memory system prevents costly system shutdowns for correctable memory errors...
US20130047045 ERROR INDICATOR FROM ECC DECODER  
The subject disclosure provides a method for generating a read-level error signal, comprising, correcting a plurality of bits read from a flash memory, determining a first error rate of a first...
US20080195899 Apparatus and method for deciding adaptive target packet error rate in wireless communication system  
An apparatus and method for deciding a target Packet Error Rate (PER) in a wireless communication system are provided. The method includes setting a target PER, comparing a variance of the target...
US20080215935 Processing Configuration Data Frames  
In at least some embodiments, a Programmable Logic Device (PLD) is configured to using a counter in conjunction with a threshold value to determine whether a configuration data frame is to be...
US20130159796 READ BIAS MANAGEMENT TO REDUCE READ ERRORS FOR PHASE CHANGE MEMORY  
Subject matter disclosed herein relates to a memory device, and more particularly to read performance of phase change memory.
US20120198290 NON-VOLATILE MEMORY DEVICE AND PROGRAMMING METHOD THEREOF  
A method for performing a program operation in a non-volatile memory device includes applying a programming pulse to a plurality of memory cells, verifying whether the plurality of the memory...
US20130166972 Apparatus and Methods of Programming Memory Cells using Adjustable Charge State Level(s)  
Apparatus and methods are disclosed, including a method of programming involving determining an error rate for the memory cells, and programming the memory cells using a charge state level for a...
US20120284575 ADAPTIVE MEMORY SCRUB RATE  
In one embodiment an example apparatus includes a memory with an error detection system (EDS) that detects an error event in the memory. The error event involves at least one bit in the memory...
US20140325294 SYSTEM AND METHOD OF ENHANCING DATA RELIABILITY  
In a system and method of enhancing data reliability, a reference value associated with error count is obtained, and an error count of data stored in a buffer is obtained whenever an event is...
US20140258796 DETERMINATION OF OPTIMUM THRESHOLD VOLTAGE TO READ DATA VALUES IN MEMORY CELLS  
An adaptive search scheme leads to threshold voltages that have lower bit error rates over initial values. An initial reference voltage is used and data is measured for set steps in voltage about...
US20120239991 APPARATUS AND METHOD FOR DETERMINING AN OPERATING CONDITION OF A MEMORY CELL BASED ON CYCLE INFORMATION  
Disclosed is an apparatus and method for adjusting a memory parameter in a non-volatile memory circuit. On a trigger event, a parameter is determined in accordance with a circuit characteristic...
US20170068580 ESTIMATING BIT ERROR RATE  
A system may obtain a current bit error count that identifies a quantity of bit errors in a bit stream during a time interval. The system may determine that the current bit error count identifies...
US20150333866 LINK SPEED DOWNSHIFTING FOR ERROR DETERMINATION AND PERFORMANCE ENHANCEMENTS  
Various embodiments for regulating link speed for performance enhancement and port diagnosis are provided. In response to identifying an amount of errors in a communications link above a...
US20150261599 DATA COMMUNICATION DEVICE, DATA COMMUNICATION SYSTEM AND DATA COMMUNICATION METHOD  
A data communication device includes a plurality of ports for transmitting and receiving a plurality of data strings for which sequential order is specified, transmitting means for transmitting...
US20140026003 FLASH MEMORY READ ERROR RATE REDUCTION  
An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) generate a reference voltage used by a memory circuit in a first read of a set of...
US20130219234 Data Integrity Field (DIF) Implementation with Error Detection and Intelligent Recovery Mechanism  
An apparatus for providing a data integrity field implementation in a data processing system includes a controller operative to interface between a host device and a destination device in the data...
US20130024736 PROGRAMMING ERROR CORRECTION CODE INTO A SOLID STATE MEMORY DEVICE WITH VARYING BITS PER CELL  
Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates...
US20120331357 METHOD AND SYSTEM OF COMPRESSING RAW FABRICATION DATA FOR FAULT DETERMINATION  
The instant disclosure relates to a raw data compression method for the fabrication process. The method includes the steps of: inputting into a signal converter a collection of raw data points...
US20120272106 MLC Self-RAID Flash Data Protection Scheme  
A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each...
US20120159270 MEMORY DEVICES AND METHODS FOR MANAGING ERROR REGIONS  
Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for repartitioning the stack of memory dies...
US20110219274 MEMORY SYSTEM AND METHOD FOR PREVENTING SYSTEM HANG  
A memory system includes an error detection circuit having an error counter. When a bit error rate (BER) determined by the error counter exceeds a reference BER, the memory system reduces the BER...
US20110179318 APPARATUS, A METHOD AND A PROGRAM THEREOF  
An apparatus and method for efficiently processing memory faults. A faulty memory is exchanged with a spare memory when the total number of faults in the memories is over a threshold. After the...
US20110161748 Systems, methods, and apparatuses for hybrid memory  
Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory...
Matches 1 - 45 out of 45