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US20140122947 Sequential Circuit with Error Detection  
Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate...
US20110258494 Method for Correcting Prediction Errors of Signal Values with Time Variation Subjected to Interference by Various Uncontrollable Systematic Effects  
A method for correcting the prediction of values of signal with time variation, in particular for navigation messages sent by the global satellite navigation systems, includes the following steps...
US20090210756 FRAME RESTORATION METHOD, FRAME RESTORATION CIRCUIT, AND STORAGE MEDIUM  
A restoration frame identifier monitoring unit checks restoration frame identifiers within split frames and carries out processing to divide inputted split frames for input to a first split frame...
US20090259893 10GBase-T training algorithm  
A method of identifying and correcting each of the changes that may occur with wire pairs between the transmitter and receiver in Ethernet 10GBase-T cabling is provided. The method includes four...
US20060242473 Phase optimization for data communication between plesiochronous time domains  
A method and apparatus for optimizing data transfer between launch and capture domains driven by plesiochronous launch and capture clocks transmits a beacon of representational data from the...
US20140359380 RUNTIME DYNAMIC PERFORMANCE SKEW ELIMINATION  
For runtime dynamic performance skew elimination in a computer environment, an exemplary computer environment is configured for calculating a rank heats by utilizing a plurality of fine-grained...
US20080126888 Skew-Correcting Apparatus using External Communications Element  
This algorithm and apparatus provides the ability to determine the amount of skew that should be injected into a high-speed data communications system consisting of a plurality of lanes comprising...
US20060156080 Method for the thermal testing of a thermal path to an integrated circuit  
According to one embodiment of the present invention, a method for detecting a defect in an integrated circuit using an optimized power pulse includes applying a first pulse of power to a first...
US20070088990 System and method for reduction of rebuild time in raid systems through implementation of striped hot spare drives  
The present invention is a system for reducing rebuild time in a RAID (Redundant Array of Independent Disks) configuration. The system includes a plurality of RAID disk drives, a plurality of hot...
US20060156081 Semiconductor component test procedure, as well as a data buffer component  
A data buffer component and a semiconductor component test procedure for testing a memory module are provided. At least one memory component with a series-connected buffer is included. The...
US20070113119 High-Speed Transceiver Tester Incorporating Jitter Injection  
A tester for testing high-speed serial transceiver circuitry. The tester includes a jitter generator that uses a rapidly varying phase-selecting signal to select between two or more differently...
US20060190776 Method and device for generating and detecting a fingerprint functioning as a trigger marker in a multimedia signal  
This invention relates to a device and a method of relating one or more trigger actions with a multimedia signal and corresponding method and device for detecting one or more trigger actions in a...
US20120202440 DISTORTION COMPENSATION DEVICE, TRANSMITTER, AND DISTORTION COMPENSATION METHOD  
A distortion compensation device includes a distortion compensator that predistorts an input signal based on delay signals and distortion compensation coefficients corresponding to the respective...
US20080130811 CIRCUIT AND METHOD FOR REMOVING SKEW IN DATA TRANSMITTING/RECEIVING SYSTEM  
A data transmission/reception system can lessen a skew between data and clock signal by substantially reducing a data reception error. The data transmission/reception system using a first clock...
US20100023816 METHOD FOR DETERMINING AN ASYMMETRICAL SIGNAL LAG OF A SIGNAL PATH INSIDE AN INTEGRATED CIRCUIT  
A device has at least one integrated signal path having a measurable asymmetrical signal lag and/or jitter, an output signal of the integrated signal path being able to be decoupled in a first...
US20050235177 Path delay test method  
From layout information which was generated from a net list of a semiconductor integrated circuit, extracted are a critical path to guaranteed operating frequency and physical information such as...
US20150227440 INTERFACE CALIBRATION USING CONFIGURABLE ON-DIE TERMINATIONS  
A method includes communicating over an interface between a controller and multiple memory dies, which comprise respective on-die terminations (ODTs) that are each connectable to the interface by...
US20090235127 Time lag measuring device, distance measuring apparatus and distance measuring method  
In measuring a certain time lag between generations of two pulse signals, a time lag measuring device prevents errors in measurement results even with an error in two reference signals for...
US20140173367 SYSTEMS AND METHODS FOR DIFFERENTIAL PAIR IN-PAIR SKEW DETERMINATION AND COMPENSATION  
In accordance with embodiments of the present disclosure, an information handling system may include a processor, a first information handling resource communicatively coupled to the processor,...
US20100192027 COMPENSATION OF MISMATCH ERRORS IN A TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER  
A method for the compensation of frequency-response mismatch errors in M-channel time-interleaved ADCs. The compensation is done utilizing a technique that makes use of a number of fixed filters,...
US20130091392 Apparatus and Method to Measure Timing Margin in Clock and Data Recovery System Utilizing a Jitter Stressor  
A method and a system for accurately calculating the timing margin in a clock and data recovery system (CDR) is provided that utilizes a singular path environment of hardware. The method entails...
US20090158100 JITTER APPLYING CIRCUIT AND TEST APPARATUS  
There is provided a jitter applying circuit that includes: a signal transmission path that transmits a signal from an input end to an output end thereof; a jitter control section that outputs,...
US20110302465 MISALIGNMENT COMPENSATION FOR PROXIMITY COMMUNICATION  
In a proximity communication system, transmit elements on one chip are aligned with receive elements on a second chip juxtaposed with the first chip. However, if the elements are misaligned,...
US20080010565 Data Transceiver and method thereof  
A data transceiver and method thereof are disclosed. The data transceiver generates a gated control signal according to a valid signal and a clock signal. The packets are outputted according to...
US20090109047 Skew adjusting apparatus, transmitting and receiving system, and skew adjusting method  
A skew adjusting apparatus includes: latching circuits that latch other signals in synchronism with transition timing of the signal level of a reference signal among signals transmitted with a...
US20120278669 RUNTIME DYNAMIC PERFORMANCE SKEW ELIMINATION  
For runtime dynamic performance skew elimination in a computer environment, an exemplary computer environment is configured for calculating a rank heats by utilizing a plurality of fine-grained...
US20120278668 RUNTIME DYNAMIC PERFORMANCE SKEW ELIMINATION  
For runtime dynamic performance skew elimination in a computer environment, an exemplary computer environment is configured for calculating a rank heats by utilizing a plurality of fine-grained...
US20060041796 Method and apparatus for eliminating errors in a seek operation on a recording medium  
A method and apparatus for eliminating errors in a seek operation on a recording medium are provided. Given a target address on a recording medium, a reading device is moved to seek the target...
US20090055694 APPARATUS AND METHOD FOR MEASURING SKEW IN SERIAL DATA COMMUNICATION  
An apparatus and method measures the skew between signals on data and clock channels using a bit pattern matching technique for any given protocol in Serial data communication. In one embodiment,...
US20060236157 Calibrating automatic test equipment  
Calibrating automatic test equipment (ATE) includes determining an offset between a reference timing event and a channel event, where the channel event is associated with a communication channel...
US20100115349 MISALIGNMENT COMPENSATION FOR PROXIMITY COMMUNICATION  
In a proximity communication system, transmit elements on one chip are aligned with receive elements on a second chip juxtaposed with the first chip. However, if the elements are misaligned,...
US20070234133 Device and method for testing memory access time using PLL  
A device and method for testing memory access times of a memory using a phase-locked loop (PLL) are described. The device for testing the memory access time of a memory may include a PLL and a...
US20100318860 INFORMATION PROCESSING APPARATUS, SYNCHRONIZATION CORRECTION METHOD AND COMPUTER PROGRAM  
An information processing apparatus is provided which includes a transmission unit for transmitting a query request for querying another device for a count value held by such other device, a...
US20070079180 Method and an apparatus for frequency measurement  
The frequency of the signal under test is measured by measuring the time of a prescribed phase of the signal under test, and calculating the slope of the approximate line related to...
US20140365835 Receiver Bit Alignment for Multi-Lane Asynchronous High-Speed Data Interface  
The invention uses a PRBS pattern generated by transmitter (serializer) as training At the receiver side, following receiver outputs, a synchronous capturing module is used to capture multiple...
US20110185238 MICROCOMPUTER, SEMICONDUCTOR DEVICE, AND MICROCOMPUTER APPLIED EQUIPMENT  
In plural analog circuits that can operate in parallel and are coupled to a common analog power supply terminal, one analog circuit is controlled in the analog operation start according to timing...
US20100275072 CORRECTING APPARATUS, PDF MEASUREMENT APPARATUS, JITTER MEASUREMENT APPARATUS, JITTER SEPARATION APPARATUS, ELECTRIC DEVICE, CORRECTING METHOD, PROGRAM, AND RECORDING MEDIUM  
There is provided a correcting apparatus for correcting a PDF obtained from a measurement result of measuring a characteristic of a measurement target at strobe timings including errors with...
US20100205488 FAST PHASE-FREQUENCY DETECTOR ARRANGEMENT  
The present invention relates to a detector arrangement and a charge pump circuit for a recovery circuit recovering timing information for random data. The detector arrangement comprises first...
US20100153792 Circuit and method for correcting skew in a plurality of communication channels for communicating with a memory device, memory controller, system and method using the same, and memory test system and method using the same  
In a circuit and method for correcting skew among a plurality of communication channels used in communicating with a memory circuit, and in a memory controller and memory controlling method, and...
US20170023646 TUNING A TESTING APPARATUS FOR MEASURING SKEW  
Embodiments herein discuss tuning a testing apparatus to better match the input response of a target system in which a cable will be used. For example, conductors in the cable may have a different...
US20160363625 SYMBOL TIMING RECOVERY SCHEME FOR PARALLEL RECORDING CHANNEL SYSTEMS  
A computer program product is provided for performing symbol timing recovery in a parallel recording channel system. The computer program product comprises a computer readable storage medium...
US20160034338 SEQUENTIAL CIRCUIT WITH ERROR DETECTION  
Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate...
US20150293175 METHOD AND APPARATUS FOR PERFORMING DE-SKEW CONTROL  
A method and apparatus for performing de-skew control are provided, where the method is applied to an electronic device. The method includes the steps of: performing a symbol detection at a...
US20150212157 DE-SKEWING TRANSMITTED DATA  
Techniques for de-skewing transmitted data are described herein. In one example, a method can include detecting, via a processor, a number of data lanes that transmit data. The method can also...
US20150206560 CIRCUIT FOR CONTROLLING WRITE LEVELING OF A TARGET MODULE AND A METHOD THEREOF  
A write leveling control method which includes registering data-related signal (DRS) reference delay values corresponding to types of memory modules in a leveling reference table; transmitting...
US20150046760 MEMORY CHANNEL HAVING DESKEW SEPARATE FROM REDRIVE  
A memory module may have a redrive circuit having a plurality of redrive paths, a memory device, and a deskew circuit. The deskew circuit may be separate from the plurality of redrive paths. The...
US20150006980 CIRCUITS FOR DYNAMICALLY ADAPTIVE BIT-LEVELING BY SWEEP SAMPLING WITH AUTOMATIC JITTER AVOIDANCE  
A circuit and method for implementing a adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is...
US20140006883 SYSTEM AND METHOD FOR ALIGNING DATA BITS  
Systems and methods are disclosed for aligning multiple data bits by adjusting the timing of input lines for those data bits. Embodiments include a hierarchical structure for comparing the timing...
US20130268814 DESKEW APPARATUS AND METHOD FOR PERIPHERAL COMPONENT INTERCONNECT EXPRESS  
Disclosed herein are a deskew apparatus and method for Peripheral Component Interconnect (PCI) Express for compensating for a skew. The deskew apparatus includes a lane data input unit, a lane...
US20130111278 MULTI-CHANNEL APPARATUS AND HARDWARE PHASE SHIFT CORRECTION METHOD THEREFOR  
A hardware phase shift correction method for a multi-channel apparatus is provided. The method includes the following steps. A multi-channel apparatus including a plurality of analog circuits is...

Matches 1 - 50 out of 56 1 2 >