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US20100275071 VALIDATION OF COMPUTER INTERCONNECTS  
A method of validating multi-cluster computer interconnects includes calculating a cable interconnect table associated with the multi-cluster computer, and distributing the cable interconnect...
US20140250338 VIRTUAL FUNCTION TIMEOUT FOR SINGLE ROOT INPUT/OUTPUT VIRTUALIZATION CONTROLLERS  
Systems and methods presented herein provide for resetting a controller in a Single Root Input/Output Virtualization (SR-IOV) architecture. The architecture includes a physical function that...
US20140317458 EMBEDDED RESILIENT BUFFER  
Described is an apparatus that comprises: a first sequential unit; a first queue coupled in parallel to the first sequential unit such that the first queue and first sequential unit receive a...
US20140281752 REDUNDANT BUS FAULT DETECTION  
A system and method for an approach of detecting faults in a redundant bus system based upon four timers.
US20120278666 MOBILE DEVICE AND METHOD FOR CORRECTING ERRORS OCCURRING IN ATTENTION COMMANDS OF THE MOBILE DEVICE  
In a method for correcting errors occurring in attention (AT) commands of a mobile device, the mobile device includes a first user identity module (UIM) chipset, a second UIM chipset, a buffer and...
US20100269107 METHOD AND SYSTEM FOR NOTIFYING ERROR INFORMATION IN A NETWORK  
Method and application server for providing an asynchronous error notification from an application server to an application server controller in a network is provided. The method at the...
US20060184850 Apparatus for preventing bus reset when removing a device from an IEEE 1394 network  
Disclosed is an apparatus for preventing bus reset when a node is removed in an Institute of Electrical and Electronics Engineers (IEEE) 1394 network. The apparatus includes a tone signal...
US20070101207 PCI Express interface testing apparatus  
A PCI Express interface testing apparatus for testing characteristics of signal transmissions of a PCI Express interface includes a printed circuit board, a plurality of sending signal connectors,...
US20090144589 DEVICE AND METHOD FOR CONTROLLING AN EXECUTION OF A DMA TASK  
A method for controlling an execution of a first DMA task, the method includes comprises monitoring an execution of the first DMA task, the method characterized by including defining a first DMA...
US20120102372 UNIVERSAL SERIAL BUS HUB WITH WIRELESS COMMUNICATION TO REMOTE PERIPHERAL DEVICES  
A wireless USB hub for connecting a plurality of remote peripheral devices to a computer for communication therewith without the need to physically connect the peripheral devices to the hub via a...
US20120036401 SELECTION OF A DOMAIN OF A CONFIGURATION ACCESS  
A data processing system includes an input/output (I/O) host bridge to which at least one I/O adapter is coupled by an I/O link. In a register of the I/O host bridge, a configuration partitionable...
US20090292958 ELECTRONIC APPARATUS AND STATE NOTIFICATION METHOD  
According to one embodiment, an electronic apparatus includes a timing detection module which detects a timing of notification to a user in association with execution of an application, a...
US20080276133 Software-Controlled Dynamic DDR Calibration  
A system, device and method are described that provide dynamic calibration of high-speed systems, such as high-speed DDR memory systems. In accordance with certain embodiments of the invention, a...
US20090307377 Arrangements for I/O Control in a Virtualized System  
A method for controlling input and output of a virtualized computing platform is disclosed. The method can include creating a device interface definition, assigning an identifier to a paging...
US20100162054 DETECTION OF AND RECOVERY FROM AN ELECTRICAL FAST TRANSIENT/BURST (EFT/B) ON A UNIVERSAL SERIAL BUS (USB) DEVICE  
An Electrical Fast Transient/Burst (EFT/B) detection and recovery system for a Universal Serial Bus (USB) device. The system includes a USB core and a burst controller. The USB core provides...
US20100185898 INPUT/OUTPUT PROCESSOR (IOP) BASED ZSERIES EMULATION  
The emulation of a data processing I/O protocol employs a process which obviates the need to consider hardware specific functionality for which emulation is not an optimal solution. The particular...
US20120290885 OVERSAMPLED CLOCK AND DATA RECOVERY WITH EXTENDED RATE ACQUISITION  
In described embodiments, a transceiver supports two or more rates using an oversampling clock and data recovery (CDR) circuit sampling high rate data with a predetermined CDR sampling clock. A...
US20110296255 INPUT/OUTPUT DEVICE INCLUDING A MECHANISM FOR ERROR HANDLING IN MULTIPLE PROCESSOR AND MULTI-FUNCTION SYSTEMS  
An I/O device includes a host interface that may be configured to receive and process a plurality of transaction packets sent by a number of processing units, with each processing unit...
US20100268998 MASTER/SLAVE COMMUNICATION SYSTEM  
A master includes a unit configured to register, for each slave, an expected communication time needed to exchange control data; a unit configured to register a slave in which a communication...
US20150248373 BIT ALLOCATION OVER A SHARED BUS TO FACILITATE AN ERROR DETECTION OPTIMIZATION  
Various aspects directed towards facilitating an error detection optimization over a shared bus are disclosed. A master device is coupled to a slave device, and an encoded communication of a word...
US20140281753 Systems, Apparatuses, and Methods for Handling Timeouts  
Systems, apparatuses, and method for handling timeouts in a link state training sequence are described. All modules of a port undergoing link state training placed into an intermediate state prior...
US20170097903 SYNCHRONOUS INPUT/OUTPUT USING A LOW LATENCY STORAGE CONTROLLER CONNECTION  
Aspects include transmitting a synchronous I/O command to a persistent storage control unit (SCU in response to a synchronous I/O request from an operating system (OS). A unit of work in the OS...
US20170083425 DETECTION SYSTEM AND METHOD FOR BASEBOARD MANAGEMENT CONTROLLER  
A detection system for a baseboard management controller (BMC) provides a motherboard and a BMC. The motherboard sends a detection command to the BMC, the command requiring the BMC to send a...
US20170017559 SYSTEM AND METHOD OF MONITORING A SERIAL BUS  
A system and method are provided for managing internal-computer system communications in an SPI management system. The system includes a storage device, at least one serial bus interface to...
US20160217028 Methods for Data Acquisition Systems in Real Time Applications  
A system may include a processing unit executing program instructions (SW), a data acquisition (DAQ) hardware device for acquiring sample data and/or generating control signals, and host memory...
US20160210255 INTER-PROCESSOR BUS LINK AND SWITCH CHIP FAILURE RECOVERY  
A system is disclosed in which the system may include multiple bus switches, and multiple processors. Each processor may be coupled to each bus switch. Each processor may be configured to initiate...
US20160179738 METHOD, APPARATUS AND SYSTEM FOR INTEGRATING DEVICES IN A ROOT COMPLEX  
In an embodiment, an apparatus comprises: a semiconductor die including but not limited to: at least one core to execute instructions; an agent to perform at least one function; a root complex...
US20160179610 ERROR HANDLING IN TRANSACTIONAL BUFFERED MEMORY  
Data is sent from a memory buffer device to a host device over a link. An error in the data is determined. A read response cancellation signal is sent to the host device to indicate the error to...
US20160170823 CLOUD ALERT TO REPLICA  
Systems, methods, and computer readable storage mediums for generating an alert on a failure of a storage subsystem to phone home to the cloud in a replication environment. A dataset is replicated...
US20160117215 SYSTEM AND METHOD FOR DYNAMIC BANDWIDTH THROTTLING BASED ON DANGER SIGNALS MONITORED FROM ONE MORE ELEMENTS UTILIZING SHARED RESOURCES  
A method and system for adjusting bandwidth within a portable computing device based on danger signals monitored from one on more elements of the portable computing device are disclosed. A danger...
US20160077799 CONTROL DEVICE AND CONTROL METHOD  
A control device includes a first processor, a relay device, a second processor, and a third processor. The first processor is configured to perform data communications with an electronic device....
US20160041862 METHOD AND SYSTEM FOR TIMEOUT MONITORING  
Embodiments relate to systems and methods for timeout monitoring of concurrent commands or parallel communication channels comprising assigning or de-assigning each one of the commands or...
US20150355989 SAFETY NODE IN INTERCONNECT DATA BUSES  
In safety-critical computer systems, fault tolerance is an important design requirement. Data buses for on-chip interconnection in these processor-based systems are exposed to risk arising from...
US20150331773 SIDEBAND LOGIC FOR MONITORING PCIe HEADERS  
Disclosed is a system and method for monitoring PCIe packets between clock domains. An interrupt is set to a root complex or external hardware based on the detection of malformed, and illegal,...
US20150019919 STORAGE CONTROL DEVICE AND CONTROL DEVICE FOR DETECTING ABNORMALITY OF SIGNAL LINE  
A controller module (CM) includes buffers that feed back signals output using respective signal lines used for mutual communication with other CM, and a first detecting unit and a second detecting...
US20110209009 Distributed Memory Usage for a System Having Multiple Integrated Circuits Each Including Processors  
A plurality of integrated circuits in a system, each having a program memory loaded with different sections of a program, and a second memory. The integrated circuits perform the program, such...
US20100306602 SEMICONDUCTOR DEVICE AND ABNORMALITY DETECTING METHOD  
A semiconductor device comprises: a task state storage configured to store an executing state of a processing task of software executed by a CPU and to output an executing state signal to show the...
Matches 1 - 37 out of 37