Matches 1 - 29 out of 29
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US20090300419 REALTIME TEST RESULT PROMULGATION FROM NETWORK COMPONENT TEST DEVICE  
The technology disclosed relates to real-time collection and flexible reporting of test data. In particular, it is useful when collecting packet counts during tests of network devices that simulate...
US20090287959 SYSTEM AND METHOD FOR TESTING COMPUTER  
A test system includes at least one computer and a control circuit for testing the computer. The computer includes an input interface and an output interface. The control circuit is configured for...
US20090259888 APPARATUS FOR DISPLAYING BIOS POST CODE AND METHOD THEREOF  
An apparatus for displaying a basic input output system (BIOS) power-on self-test (POST) code and a method thereof are provided. The apparatus includes a BIOS, a conversion module, and an output...
US20090235120 Systems and methods for testing a peripheral interfacing with a processor according to a MIPI protocol  
Systems and methods for testing a peripheral in accordance with a MIPI protocol are provided. A test system can test a peripheral by providing user-specified control over a test processor (which is...
US20090222695 SYSTEM AND METHOD FOR SHARING A COMMUNICATIONS LINK BETWEEN MULTIPLE COMMUNICATIONS PROTOCOLS  
A system and method for sharing a communications link between multiple protocols is described that comprises a system comprising a communications interface configured to exchange information with...
US20090222652 EMBEDDED MEMORY PROTECTION  
One embodiment of the present application includes a microcontroller ( 30 ) that has an embedded memory ( 46 ), a programmable processor ( 32 ), and a test interface ( 34 ). The memory ( 46 ) is...
US20090217093 Fault Diagnosis of Serially-Addressed Memory Modules on a PC Motherboard  
A test adaptor board connects to a personal computer (PC) motherboard that tests a memory module in a test socket. A standard memory module socket is removed from a target DRAM module slot on the...
US20090164846 Fault Injection In Dynamic Random Access Memory Modules For Performing Built-In Self-Tests  
Fault injection in dynamic random access memory (‘DRAM’) modules for performing built-in self-tests (‘BISTs’) including establishing, in the mode registers of the DRAM modules by the memory...
US20090158092 SYSTEM AND METHOD FOR INDICATING STATUS OF AN ON-CHIP POWER SUPPLY SYSTEM  
The status of multiple on-chip power supply systems is indicated for use in modifying chip test flow and diagnosing chip failure. Digital compliance signals are received, each compliance signal...
US20090055685 Electronic apparatus in which functioning of of a microcomputer is monitored by another microcomputer to detect abnormal operation  
In an electronic apparatus, a first microcomputer is monitored by a second microcomputer, which periodically transmits data relating to a main function to the first microcomputer to be processed....
US20090013214 ON-CHIP SAMPLERS FOR ASYNCHRONOUSLY TRIGGERED EVENTS  
Embodiments of an integrated circuit that includes a debug circuit are described. This debug circuit is configured to test an asynchronous circuit by performing analog measurements on asynchronous...
US20080307261 ACTIVATING A DESIGN TEST MODE IN A GRAPHICS CARD HAVING MULTIPLE EXECUTION UNITS  
Provided are a method and system for activating a design test mode in a graphics card having multiple execution units. A design test mode is activated in a graphics module comprising multiple...
US20080301500 System and Method for Identifying and Manipulating Logic Analyzer Data from Multiple Clock Domains  
A system and method for identifying and manipulating logic analyzer data from multiple clock domains is presented. A logic analyzer receives debug data and determines whether the debug data is a...
US20080282110 SCAN CLOCK ARCHITECTURE SUPPORTING SLOW SPEED SCAN, AT SPEED SCAN, AND LOGIC BIST  
Herein described are at least a method and a system to perform scan testing of an integrated circuit chip using one or more internal and external clock sources. In a representative embodiment, the...
US20080263400 Fault insertion system  
A method of scheduling a simulated hardware fault on a computer system by specifying at least a termination point where the simulated hardware fault will be automatically removed from the computer...
US20080229149 REMOTE TESTING OF COMPUTER DEVICES  
In embodiments of the present invention improved capabilities are described for a method and system of software testing that may used on a computer network, the network may include a plurality of...
US20080222452 TEST APPARATUS FOR TESTING A CIRCUIT UNIT  
Test apparatus for testing a circuit unit. A first test device is arranged outside the circuit unit. A second test device, which is arranged integrally with the circuit unit, has a sample-and-hold...
US20080209270 Automation Of Testing In Remote Sessions  
Systems and methods are described for implementing automation of testing in remote sessions. In an implementation, a test agent is deployed at a remote server to automate testing of various...
US20080168310 Hardware diagnostics and software recovery on headless server appliances  
Described is a headless server appliance configured with a secondary actuation mechanism that when actuated, enters the headless server appliance into a diagnostic mode. For example, the diagnostic...
US20080148101 SYSTEM, METHOD, AND DEVICE INCLUDING BUILT-IN SELF TESTS FOR COMMUNICATION BUS DEVICE  
A method, device, and system including built-in self tests for a communication bus device is disclosed. In one form, a method of testing a device operable to be coupled to a communication port an...
US20080148100 CONTROL PANEL ASSEMBLY METHOD FOR A FITNESS EQUIPMENT METER  
The present invention is a control panel assembly method for a fitness equipment meter. The processors of the A/D module and IC module are integrated into a single processor, namely, all control...
US20080034255 PROGRAM FAILURE ANALYSIS SYSTEM, FAILURE ANALYSIS METHOD, AND EMULATOR DEVICE  
A CPU forced stop signal is used as means for stopping execution of a program executed on a ROM by a CPU of a target system. A time required for stopping the CPU from the issuance of the CPU forced...
US20080028263 Apparatus and method for protection of JTAG scan chains in a microprocessor  
In an integrated circuit processing unit having an emulation unit fabricated therewith, signal group protection apparatus is provided for prohibiting unauthorized access by the test and debug...
US20080022154 Information processing device  
The present invention provides an information processing device having a CPU which executes an OS and firmware, and a plurality of memory controllers which are connected to the CPU, control writing...
US20080022153 CONTROL CIRCUIT OF GROUND FAULT CIRCUIT INTERRUPTER (GFCI)  
A control circuit of Ground Fault Circuit Interrupter (GFCI), includes a load connection circuit used to connect power end and load end while transferring AC thereof, a creepage detection circuit,...
US20080010528 FAULTED CIRCUIT INDICATOR MONITORING DEVICE WITH WIRELESS MEMORY MONITOR  
A wireless communications system for viewing and modifying memory locations within a power system device is provided including a wireless device and a power system device. The wireless device...
US20080010527 Method of solving BIST failure of CPU by means of BIOS and maximizing system performance  
The present invention is to provide a method of solving BIST (Build-in Self Test) failure of CPU (Central Process Unit) by means of BIOS (Basic Input/Output System) and maximizing system...
US20080010526 IDENTIFICATION OF UNINFORMATIVE FUNCTION NAMES IN CALL-STACK TRACES  
A method for identifying names of uninformative functions in call-stack traces is described. The method comprises the steps of obtaining a set of call-stacks and information indicative of which...
US20080005617 AUTOMATED PROCESSING OF ELECTRONIC LOG BOOK PILOT REPORTS FOR GROUND-BASED FAULT PROCESSING  
Automated processing of electronic log book (ELB) pilot reports (PIREPs) are configured to receive ELB PIREPs and prioritize observed faults and potential observed faults included in the ELB...
Matches 1 - 29 out of 29