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US20130036473 |
SYSTEM AND METHOD FOR BRANCH FUNCTION BASED OBFUSCATION
Disclosed herein are systems, methods, and non-transitory computer-readable storage media for obfuscating branches in computer code. A compiler or a post-compilation tool can obfuscate branches by...
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US20110238956 |
Collective Acceleration Unit Tree Structure
A mechanism is provided in a collective acceleration unit for performing a collective operation to distribute or collect data among a plurality of participant nodes. The mechanism receives an input...
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US20100306512 |
COMPILER TECHNIQUE FOR EFFICIENT REGISTER CHECKPOINTING TO SUPPORT TRANSACTION ROLL-BACK
A method and apparatus for efficient register checkpointing is herein described. A transaction is detected in program code. A recovery block is inserted in the program code to perform recovery...
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US20110022833 |
ALTERING PERFORMANCE OF COMPUTATIONAL UNITS HETEROGENEOUSLY ACCORDING TO PERFORMANCE SENSITIVITY
One or more computational units of a computer system are selectively altered in terms of performance according to which of the one or more computational units has a higher performance sensitivity...
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US20120124350 |
TABLE-DRIVEN SOAKER TOOL FOR INFORMATION HANDLING SYSTEMS
A soaker tool for an information handling system (IHS) exercises the IHS to provide a predetermined amount of utilization that a user may specify. The soaker tool schedules wait times following...
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US20130036296 |
FLOATING POINT EXECUTION UNIT WITH FIXED POINT FUNCTIONALITY
A floating point execution unit is capable of selectively repurposing one or more adders in an exponent path of the floating point execution unit to perform fixed point addition operations, thereby...
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US20110093684 |
TRANSPARENT CONCURRENT ATOMIC EXECUTION
Executing a block of code is disclosed. Executing includes receiving an indication that the block of code is to be executed using a synchronization mechanism and speculatively executing the block...
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US20110314251 |
MEMORY SAFETY OF FLOATING-POINT COMPUTATIONS
Concepts and technologies are described herein for determining memory safety of floating-point computations. The concepts and technologies described herein analyze code to determine if any...
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US20120124348 |
BRANCH PREDICTOR ACCURACY BY FORWARDING TABLE UPDATES TO PENDING BRANCH PREDICTIONS
A method and apparatus are provided for increasing the accuracy of a branch predictor. A branch prediction table provides a first instance of a branch prediction value associated with an...
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US20120290818 |
Split Scheduler
In an embodiment, a scheduler implements a first dependency array that tracks dependencies on instruction operations (ops) within a distance N of a given op and which are short execution latency...
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US20120290816 |
Optimized Scalar Promotion with Load and Splat SIMD Instructions
Mechanisms for optimizing scalar code executed on a single instruction multiple data (SIMD) engine are provided. Placement of vector operation-splat operations may be determined based on an...
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US20110252222 |
EVENT COUNTER IN A SYSTEM ADAPTED TO THE JAVACARD LANGUAGE
The implementation of a counter in a microcontroller adapted to the JavaCard language while respecting the atomicity of a modification of the value of this counter, wherein the counter is reset by...
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US20120246452 |
Signature Update by Code Transformation
Embodiments described herein provide an apparatus, computer readable digital storage medium and method for producing an instruction sequence for a computation unit which can be controlled by a...
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US20110161638 |
Ising Systems: Helical Band Geometry For DTC and Integration of DTC Into A Universal Quantum Computational Protocol
Disclosed herein are efficient geometries for dynamical topology changing (DTC), together with protocols to incorporate DTC into quantum computation. Given an Ising system, twisted depletion to...
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US20120331271 |
COMPRESSED INSTRUCTION FORMAT
A technique for decoding an instruction in an a variable-length instruction set. In one embodiment, an instruction encoding is described, in which legacy, present, and future instruction set...
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US20120284490 |
WORKING SET PROFILER
A working set profiler can monitor an execution of a program or can monitor a user-specified portion of a program to identify methods executed within the monitored execution and associate memory...
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US20120204017 |
Microprocessor for Executing Byte Compiled Java Code
A microprocessor architecture for executing byte compiled Java programs directly in hardware. The microprocessor targets the lower end of the embedded systems domain and features two orthogonal...
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US20110145548 |
MICROPROCESSOR FOR EXECUTING BYTE COMPILED JAVA CODE
A microprocessor architecture for executing byte compiled Java programs directly in hardware. The microprocessor targets the lower end of the embedded systems domain and features two orthogonal...
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US20110107071 |
SYSTEM AND METHOD FOR USING A BRANCH MIS-PREDICTION BUFFER
A system and method is provided for executing a conditional branch instruction. The system and method may include a branch predictor to predict one or more instructions that depend on the...
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US20100299504 |
MICROPROCESSOR WITH MICROINSTRUCTION-SPECIFIABLE NON-ARCHITECTURAL CONDITION CODE FLAG REGISTER
A microprocessor includes an architectural register and a non-architectural register, each having a plurality of condition code flags. A first instruction of the microarchitectural instruction set...
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US20120124349 |
POWER EFFICIENT PATTERN HISTORY TABLE FETCH IN BRANCH PREDICTOR
A method and apparatus for branch prediction is disclosed. A pattern history table (PHT) is accessed based on at least one global history value to obtain a prediction value. The prediction value...
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US20130086370 |
COMBINED BRANCH TARGET AND PREDICATE PREDICTION
Embodiments provide methods, apparatus, systems, and computer readable media associated with predicting predicates and branch targets during execution of programs using combined branch target and...
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US20120159126 |
Programming Language Exposing Idiom Calls
A programming language may include hint instructions that may notify a programming idiom accelerator that a programming idiom is coming. An idiom begin hint exposes the programming idiom to the...
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US20120060018 |
Collective Operations in a File System Based Execution Model
A mechanism is provided for group communications using a MULTI-PIPE synthetic file system. A master application creates a multi-pipe synthetic file in the MULTI-PIPE synthetic file system, the...
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US20110238949 |
Distributed Administration Of A Lock For An Operational Group Of Compute Nodes In A Hierarchical Tree Structured Network
Distributed administration of a lock for an operational group of compute nodes in a hierarchical tree structured network including assigning the root node of the operational group to send...
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US20110173413 |
EMBEDDING GLOBAL BARRIER AND COLLECTIVE IN A TORUS NETWORK
Embodiments of the invention provide a method, system and computer program product for embedding a global barrier and global interrupt network in a parallel computer system organized as a torus...
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US20120151193 |
OPTIMIZED BUFFER PLACEMENT BASED ON TIMING AND CAPACITANCE ASSERTIONS
A method is provided for optimized buffer placement based on timing and capacitance assertions in a functional chip unit including a single source and multiple macros, each having a sink. Placement...
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US20100306515 |
Predictors with Adaptive Prediction Threshold
An adaptive prediction threshold scheme for dynamically adjusting prediction thresholds of entries in a Pattern History Table (PHT) by observing global tendencies of the branch or branches that...
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US20120072701 |
Method Macro Expander
One embodiment of the present invention sets forth a [TODO once claims are reviewed]
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US20110173417 |
Programming Idiom Accelerators
A wake-and-go mechanism may be a programming idiom accelerator. As a processor fetches instructions, the programming idiom accelerator may look ahead to determine whether a programming idiom is...
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US20120084538 |
Methodology and Framework for Run-Time Coverage Measurement of Architectural Events of a Microprocessor
A post-silicon testing apparatus, method, and computer program product provide for runtime coverage measurement methodology to measure the architectural events in hardware. Measurement of all...
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US20090287907 |
System for providing trace data in a data processor having a pipelined architecture
The invention is a method and system for providing trace data in a pipelined data processor. Aspects of the invention include providing a trace pipeline in parallel to the execution pipeline,...
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US20110271082 |
PERFORMING ACTIONS ON FRAME ENTRIES IN RESPONSE TO RECEIVING BULK INSTRUCTION
Various example embodiments are disclosed. According to an example embodiment, a switch may comprise an instruction decode stage and a lookup stage. The instruction decode stage may be configured...
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US20130080744 |
ABSTRACTING COMPUTATIONAL INSTRUCTIONS TO IMPROVE PERFORMANCE
Methods and systems for executing a code stream of non-native binary code on a computing system are disclosed. One method includes parsing the code stream to detect a plurality of elements...
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US20100332810 |
Reconfigurable Functional Unit Having Instruction Context Storage Circuitry To Support Speculative Execution of Instructions
A functional unit is described. The functional unit includes a reconfigurable logic circuitry and instruction context storage circuitry to store instruction context information generated from...
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US20120054472 |
AUTOMATIC IDENTIFICATION OF BOTTLENECKS USING RULE-BASED EXPERT KNOWLEDGE
Execution states of tasks are inferred from collection of information associated with runtime execution of a computer system. Collection of information may include infrequent samples of executing...
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US20120173855 |
Exception Transporting and Handling of Concurrent Exceptions
Methods and systems for handling exceptions, including being provided with a catch list, the catch list being a flattened inheritance tree for exception types in ascending inheritance order,...
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US20130067204 |
Instructions With Floating Point Control Override
Methods and apparatus relating to instructions with floating point control override are described. In an embodiment, floating point operation settings indicated by a floating point control register...
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US20100005316 |
BRANCH TRACE METHODOLOGY
Method, system, and computer program product embodiments for performing a branch trace operation on a computer system of an end user are provided. An encrypted mapping macro is provided to the end...
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US20110314261 |
Prefetch of Attributes in Evaluating Access Control Requests
In an embodiment, a method is provided for prefetching attributes used in access control evaluation. In this method, an access control policy that comprises rules is retrieved. These rules further...
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US20130097406 |
CLUSTER COMPUTING USING SPECIAL PURPOSE MICROPROCESSORS
In some embodiments, a computer cluster system comprises a plurality of nodes and a software package comprising a user interface and a kernel for interpreting program code instructions. In certain...
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US20050149912 |
Dynamic online optimizer
A system and method for optimizing a series of traces to be executed by a processing core is disclosed. The lines of a trace are sent to an optimizer each time they are sent to a processing core to...
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US20130067197 |
COMPUTER SUBSYSTEM AND COMPUTER SYSTEM
The present invention provides a computer subsystem and a computer system. The computer subsystem includes L composite nodes, each composite node includes M basic nodes, each basic node includes N...
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US20110320793 |
OPERATING SYSTEM AWARE BRANCH PREDICTOR USING A DYNAMICALLY RECONFIGURABLE BRANCH HISTORY TABLE
A processor resource manager assigns a branch history resource to a first execution mode. The branch history resource is utilized for predicting a branch direction of a branch instruction. Next,...
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US20110113065 |
MANAGEMENT OF RESOURCES IN A HOST SYSTEM
A computer implemented method for managing access to system resources includes receiving a request from a user for write-access to a resource in a host system, the host system including...
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US20120047495 |
EXECUTION ENVIRONMENT SUPPORT FOR REACTIVE PROGRAMMING
An execution environment is created or extended to include support for coroutines to facilitate reactive programming. Utilizing functionality provided by an execution environment, such as a virtual...
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US20120079251 |
MULTIPLY ADD FUNCTIONAL UNIT CAPABLE OF EXECUTING SCALE, ROUND, GETEXP, ROUND, GETMANT, REDUCE, RANGE AND CLASS INSTRUCTIONS
A method is described that involves executing a first instruction with a functional unit. The first instruction is a multiply-add instruction. The method further includes executing a second...
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US20100057727 |
DETECTION OF RECURRING NON-OCCURRENCES OF EVENTS USING PATTERN MATCHING
Techniques for detecting recurring non-occurrences of an event. In one embodiment, techniques are provided for detecting the non-occurrence of an event within each of a series of time periods...
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US20110131425 |
SYSTEMS AND METHODS FOR POWER MANAGEMENT IN A HIGH PERFORMANCE COMPUTING (HPC) CLUSTER
Embodiments of the invention broadly contemplate systems, methods, apparatuses and program products providing a power management technique for an HPC cluster with performance improvements for...
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US20090217012 |
MICROARCHITECTURE, METHOD AND COMPUTER PROGRAM PRODUCT FOR EFFICIENT DATA GATHERING FROM A SET OF TRACE ARRAYS
An architecture for collecting performance data in a processor, that includes: a trace read control unit and a trace data collect unit, each unit coupled to a plurality of trace array and multiplex...
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