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US20130262842 CODE GENERATION METHOD AND INFORMATION PROCESSING APPARATUS  
An information processing apparatus generates first and second trees representing a dependency relationship among instructions from first code. The information processing apparatus then adjusts the...
US20140208086 VECTOR EXCEPTION CODE  
Vector exception handling is facilitated. A vector instruction is executed that operates on one or more elements of a vector register. When an exception is encountered during execution of the...
US20130036473 SYSTEM AND METHOD FOR BRANCH FUNCTION BASED OBFUSCATION  
Disclosed herein are systems, methods, and non-transitory computer-readable storage media for obfuscating branches in computer code. A compiler or a post-compilation tool can obfuscate branches by...
US20140189292 Functional Unit Having Tree Structure To Support Vector Sorting Algorithm and Other Algorithms  
An apparatus is described having a functional unit of an instruction execution pipeline. The functional unit has a plurality of compare-and-exchange circuits coupled to network circuitry to...
US20130311758 HARDWARE PROFILING MECHANISM TO ENABLE PAGE LEVEL AUTOMATIC BINARY TRANSLATION  
A hardware profiling mechanism implemented by performance monitoring hardware enables page level automatic binary translation. The hardware during runtime identifies a code page in memory...
US20110238956 Collective Acceleration Unit Tree Structure  
A mechanism is provided in a collective acceleration unit for performing a collective operation to distribute or collect data among a plurality of participant nodes. The mechanism receives an input...
US20100306512 COMPILER TECHNIQUE FOR EFFICIENT REGISTER CHECKPOINTING TO SUPPORT TRANSACTION ROLL-BACK  
A method and apparatus for efficient register checkpointing is herein described. A transaction is detected in program code. A recovery block is inserted in the program code to perform recovery...
US20140281380 EXECUTION CONTEXT SWAP BETWEEN HETEROGENOUS FUNCTIONAL HARDWARE UNITS  
Remapping technologies for execution context swap between heterogeneous functional hardware units are described. A computing system includes multiple registers configured to store remote contexts...
US20130305019 Instruction and Logic to Control Transfer in a Partial Binary Translation System  
A dynamic optimization of code for a processor-specific dynamic binary translation of hot code pages (e.g., frequently executed code pages) may be provided by a run-time translation layer. A method...
US20110022833 ALTERING PERFORMANCE OF COMPUTATIONAL UNITS HETEROGENEOUSLY ACCORDING TO PERFORMANCE SENSITIVITY  
One or more computational units of a computer system are selectively altered in terms of performance according to which of the one or more computational units has a higher performance sensitivity...
US20140068573 Error-code and exception-based function dispatch tables  
A condition detected by a virtual routine may be treated by setting an error code or raising an exception, depending on circumstances. Enhanced vtable layouts promote availability of both...
US20120124350 TABLE-DRIVEN SOAKER TOOL FOR INFORMATION HANDLING SYSTEMS  
A soaker tool for an information handling system (IHS) exercises the IHS to provide a predetermined amount of utilization that a user may specify. The soaker tool schedules wait times following...
US20130036296 FLOATING POINT EXECUTION UNIT WITH FIXED POINT FUNCTIONALITY  
A floating point execution unit is capable of selectively repurposing one or more adders in an exponent path of the floating point execution unit to perform fixed point addition operations, thereby...
US20110093684 TRANSPARENT CONCURRENT ATOMIC EXECUTION  
Executing a block of code is disclosed. Executing includes receiving an indication that the block of code is to be executed using a synchronization mechanism and speculatively executing the block...
US20140237217 VECTORIZATION IN AN OPTIMIZING COMPILER  
An optimizing compiler includes a vectorization mechanism that optimizes a computer program by substituting code that includes one or more vector instructions (vectorized code) for one or more...
US20140019736 Embedded Branch Prediction Unit  
In accordance with some embodiments of the present invention, a branch prediction unit for an embedded controller may be placed in association with the instruction fetch unit instead of the decode...
US20110314251 MEMORY SAFETY OF FLOATING-POINT COMPUTATIONS  
Concepts and technologies are described herein for determining memory safety of floating-point computations. The concepts and technologies described herein analyze code to determine if any...
US20120124348 BRANCH PREDICTOR ACCURACY BY FORWARDING TABLE UPDATES TO PENDING BRANCH PREDICTIONS  
A method and apparatus are provided for increasing the accuracy of a branch predictor. A branch prediction table provides a first instance of a branch prediction value associated with an...
US20140075167 BRANCH HISTORY CACHE AND METHOD  
A branch history table cache is a write cache that stores values of branch history counters written to a branch history table. An update to a branch history table counter is reflected in both the...
US20120290818 Split Scheduler  
In an embodiment, a scheduler implements a first dependency array that tracks dependencies on instruction operations (ops) within a distance N of a given op and which are short execution latency...
US20120290816 Optimized Scalar Promotion with Load and Splat SIMD Instructions  
Mechanisms for optimizing scalar code executed on a single instruction multiple data (SIMD) engine are provided. Placement of vector operation-splat operations may be determined based on an...
US20130305024 METHOD AND SYSTEM USING EXCEPTIONS FOR CODE SPECIALIZATION IN A COMPUTER ARCHITECTURE THAT SUPPORTS TRANSACTIONS  
A method and system uses exceptions for code specialization in a system that supports transactions. The method and system includes inserting one or more branchless instructions into a sequence of...
US20110252222 EVENT COUNTER IN A SYSTEM ADAPTED TO THE JAVACARD LANGUAGE  
The implementation of a counter in a microcontroller adapted to the JavaCard language while respecting the atomicity of a modification of the value of this counter, wherein the counter is reset by...
US20130339709 TRANSACTION ABORT INSTRUCTION  
A TRANSACTION ABORT instruction is used to abort a transaction that is executing in a computing environment. The TRANSACTION ABORT instruction includes at least one field used to specify a...
US20130339676 TRANSACTION ABORT INSTRUCTION  
A TRANSACTION ABORT instruction is used to abort a transaction that is executing in a computing environment. The TRANSACTION ABORT instruction includes at least one field used to specify a...
US20140281377 Identifying Logical Planes Formed Of Compute Nodes Of A Subcommunicator In A Parallel Computer  
In a parallel computer, a plurality of logical planes formed of compute nodes of a subcommunicator may be identified by: for each compute node of the subcommunicator and for a number of dimensions...
US20140281374 Identifying Logical Planes Formed Of Compute Nodes Of A Subcommunicator In A Parallel Computer  
In a parallel computer, a plurality of logical planes formed of compute nodes of a subcommunicator may be identified by: for each compute node of the subcommunicator and for a number of dimensions...
US20140032882 MODIFICATION OF FUNCTIONALITY IN EXECUTABLE CODE  
In an example embodiment, an instruction set is accessed. An instruction modifier is associated with the instruction set. Thereafter, the instruction set is transformed into a modified instruction...
US20140082337 BRANCH TARGET BUFFER PRELOAD TABLE  
Embodiments relate to using a branch target buffer preload table. An aspect includes receiving a search request to locate branch prediction information associated with a branch instruction....
US20130332716 BRANCH TARGET BUFFER PRELOAD TABLE  
Embodiments relate to using a branch target buffer preload table. An aspect includes receiving a search request to locate branch prediction information associated with a branch instruction....
US20130326204 Configuration-Preserving Preprocessor and Configuration-Preserving Parser  
Methods, systems, and apparatuses, including computer programs encoded on computer readable media, for generating a plurality of tokens from one or more source files that include source code in a...
US20120246452 Signature Update by Code Transformation  
Embodiments described herein provide an apparatus, computer readable digital storage medium and method for producing an instruction sequence for a computation unit which can be controlled by a...
US20140082330 ENHANCED INSTRUCTION SCHEDULING DURING COMPILATION OF HIGH LEVEL SOURCE CODE FOR IMPROVED EXECUTABLE CODE  
Systems and methods for static code scheduling are disclosed. A method can include receiving an intermediate representation of source code, building a directed acyclic graph (DAG) for the...
US20130332714 FAST INDEX TREE FOR ACCELERATED BRANCH PREDICTION  
Embodiments relate to using a fast index tree for accelerated branch prediction. A computer-implemented method includes determining, by a computer, that searching of a branch target buffer is to be...
US20140195788 REDUCING INSTRUCTION MISS PENALTIES IN APPLICATIONS  
Embodiments include systems and methods for reducing instruction cache miss penalties during application execution. Application code is profiled to determine “hot” code regions likely to exp...
US20130262835 CODE GENERATION METHOD AND INFORMATION PROCESSING APPARATUS  
An information processing apparatus generates first and second operation trees representing a dependency relationship among the instructions included in a first code, and computes first and second...
US20140181486 BRANCH PREDICTION TABLE INSTALL SOURCE TRACKING  
Embodiments relate to branch prediction table install source tracking. An aspect includes a computer-implemented method for branch prediction table install source tracking. The method includes...
US20140281439 HARDWARE OPTIMIZATION OF HARD-TO-PREDICT SHORT FORWARD BRANCHES  
Methods and apparatuses for optimizing hard-to-predict short forward branches. A method detects a forward conditional branch with at least one instruction between the forward conditional branch and...
US20110161638 Ising Systems: Helical Band Geometry For DTC and Integration of DTC Into A Universal Quantum Computational Protocol  
Disclosed herein are efficient geometries for dynamical topology changing (DTC), together with protocols to incorporate DTC into quantum computation. Given an Ising system, twisted depletion to...
US20130290682 COMPRESSED INSTRUCTION FORMAT  
A technique for decoding an instruction in a variable-length instruction set. In one embodiment, an instruction encoding is described, in which legacy, present, and future instruction set...
US20120331271 COMPRESSED INSTRUCTION FORMAT  
A technique for decoding an instruction in an a variable-length instruction set. In one embodiment, an instruction encoding is described, in which legacy, present, and future instruction set...
US20120284490 WORKING SET PROFILER  
A working set profiler can monitor an execution of a program or can monitor a user-specified portion of a program to identify methods executed within the monitored execution and associate memory...
US20130332713 FAST INDEX TREE FOR ACCELERATED BRANCH PREDICTION  
Embodiments relate to using a fast index tree for accelerated branch prediction. A system includes a branch target buffer, a FIT structure, and a processing circuit configured to perform a method....
US20140052962 CUSTOM CHAINING STUBS FOR INSTRUCTION CODE TRANSLATION  
A processing system includes a microprocessor, a hardware decoder arranged within the microprocessor, and a translator operatively coupled to the microprocessor. The hardware decoder is configured...
US20130198496 MAJOR BRANCH INSTRUCTIONS  
Major branch instructions are provided that enable execution of a computer program to branch from one segment of code to another segment of code. These instructions also create a new stream of...
US20130198492 MAJOR BRANCH INSTRUCTIONS  
Major branch instructions are provided that enable execution of a computer program to branch from one segment of code to another segment of code. These instructions also create a new stream of...
US20140181476 Scheduler Implementing Dependency Matrix Having Restricted Entries  
A scheduler implementing a dependency matrix having restricted entries is disclosed. A processing device of the disclosure includes a decode unit to decode an instruction and a scheduler...
US20120204017 Microprocessor for Executing Byte Compiled Java Code  
A microprocessor architecture for executing byte compiled Java programs directly in hardware. The microprocessor targets the lower end of the embedded systems domain and features two orthogonal...
US20110145548 MICROPROCESSOR FOR EXECUTING BYTE COMPILED JAVA CODE  
A microprocessor architecture for executing byte compiled Java programs directly in hardware. The microprocessor targets the lower end of the embedded systems domain and features two orthogonal...
US20110107071 SYSTEM AND METHOD FOR USING A BRANCH MIS-PREDICTION BUFFER  
A system and method is provided for executing a conditional branch instruction. The system and method may include a branch predictor to predict one or more instructions that depend on the...