Matches 1 - 50 out of 146 1 2 3 >


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US20110153307 Transitioning From Source Instruction Set Architecture (ISA) Code To Translated Code In A Partial Emulation Environment  
In one embodiment, a processor can operate in multiple modes, including a direct execution mode and an emulation execution mode. More specifically, the processor may operate in a partial emulation...
US20090313461 CIRCUIT WITH A PLURALITY OF MODES OF OPERATION  
A circuit capable of being operated in a first and a second mode of operation comprises a storage location adapted to store at least a first state, a second state and a third state, wherein the...
US20110145553 ACCELERATING PARALLEL TRANSACTIONS USING CACHE RESIDENT TRANSACTIONS  
Handling parallelism in transactions. One embodiment includes a method that includes beginning a cache resident transaction. The method further includes encountering a nested structured...
US20090070566 Electronic Device With CPU and Interrupt Relay Stage  
An electronic device with a CPU configured to be switched from a low power mode into a higher power mode in response to an interrupt and an interrupt relay coupled between an interrupt generator...
US20150019847 Programmable CPU Register Hardware Context Swap Mechanism  
A central processing unit (CPU) having an interrupt unit for interrupting execution of instructions, a plurality context defining register sets, wherein each set of registers having the same...
US20080109682 INTEGRATED CIRCUIT CARD WITH CONDITION DETECTOR  
An integrated circuit card includes a central processing unit, a memory and an abnormal condition detector. The memory stores data to be processed by the central processing unit. The abnormal...
US20110231637 CENTRAL PROCESSING UNIT AND METHOD FOR WORKLOAD DEPENDENT OPTIMIZATION THEREOF  
A central processing unit (CPU) adapted for use in a computing system, such as a personal computer or other processing apparatus. The CPU is implemented to perform hyper-threading (HT), and...
US20100199118 MICROCONTROLLER WITH COMPATIBILITY MODE  
A microcontroller is operable to enable a compatibility mode where a clock source of the microcontroller is adjusted to support timing requirements of applications written for legacy...
US20100088495 MODE-SPECIFIC CONTAINER RUNTIME ATTACHMENT  
The operation of a multi-mode application. The multi-mode application has a number of mode-specific logical containers of components. Each mode-specific container contains components that assist...
US20110161627 MECHANISMS TO AVOID INEFFICIENT CORE HOPPING AND PROVIDE HARDWARE ASSISTED LOW-POWER STATE SELECTION  
An apparatus and method is described herein for avoiding inefficient core hopping and providing hardware assisted power state selection. Future idle-activity of cores is predicted. If the...
US20090182987 Processing Unit Incorporating Multirate Execution Unit  
A multirate execution unit is capable of being operated in a plurality of modes, with the execution unit being capable of clocked at multiple different rates relative to a multithreaded issue unit...
US20140164738 INSTRUCTION CATEGORIZATION FOR RUNAHEAD OPERATION  
Embodiments related to methods and devices operative, in the event that execution of an instruction produces a runahead-triggering event, to cause a microprocessor to enter into and operate in a...
US20120233477 DYNAMIC CORE SELECTION FOR HETEROGENEOUS MULTI-CORE SYSTEMS  
Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be...
US20090300420 Method for Testing at Least One Arithmetic Unit Installed in a Control Unit  
A method for testing at least two arithmetic units installed in a control unit includes: loading of first test data for testing a first arithmetic unit; saving the loaded first test data in a...
US20100218187 TECHNIQUES FOR CONTROLLING DESKTOP STATE  
Techniques for controlling desktop state are provided. Processing events are associated with desktop states and are associated with resource actions. When a desktop encounters the processing...
US20090158016 USE OF MODES FOR COMPUTER CLUSTER MANAGEMENT  
A system, method and computer program product for managing a plurality of applications in a computer cluster. Each application is able to run on a particular node in the cluster. In one...
US20050091474 Fuse configurable alternate behavior of a central processing unit  
A method, system and apparatus are provided for alternating instruction sets in central processing units. A microcontroller is provided with a configuration mechanism, such as a fuse that,...
US20140032886 MEMORY CONTROLLERS  
Methods and controllers for executing an instruction set are provided. In one such method, executing an instruction set includes executing an instruction of one type in the instruction set,...
US20100088439 INTELLIGENT CASE FOR HANDHELD COMPUTER  
An intelligent case for a handheld computer, the case including a compartment for removably housing the handheld computer; a microcontroller; a first communication device to enable communication...
US20090198979 PROCESSOR PERFORMANCE STATE OPTIMIZATION  
A processor performance state optimization includes a system to change a performance state of a processor. In an embodiment, the system to change a performance state of the processor includes a...
US20150127928 Energy Efficient Multi-Modal Instruction Issue  
A processor is described herein that is configured to switch between a first instruction issue mode of the processor and a second instruction issue mode of the processor based at least in part on...
US20050086650 Transferring execution from one instruction stream to another  
A computer has instruction pipeline circuitry capable of executing two instruction set architectures (ISA's). A binary translator translates at least a selected portion of a computer program from...
US20070022277 Method and system for an enhanced microprocessor  
Systems and methods for modes of operation for processing data are disclosed. While executing a program in one mode the hazard checking logic present in the microprocessor system may be utilized...
US20090307470 MULTI THREAD PROCESSOR HAVING DYNAMIC RECONFIGURATION LOGIC CIRCUIT  
A processor according to the present invention cyclically executes a plurality of threads, for each time period allocated thereto. The processor stores, for each thread, configuration information...
US20100153693 CODE EXECUTION WITH AUTOMATED DOMAIN SWITCHING  
Within the field of computing, many scenarios involve the execution of an instruction set within a domain that is configured to support an execution context. However, various portions of the...
US20090132796 POLLING USING RESERVATION MECHANISM  
A first thread enters a polling loop to wait for a signal from a second thread before processing instructions dependent on the polling loop. When entering the polling loop, the first thread sets a...
US20090006821 APPARATUS, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PROCESSING INFORMATION BY CONTROLLING ARITHMETIC MODE  
An HW arithmetic unit executes a predetermined arithmetic operation. An arithmetic-mode determining unit determines, based on an attribute or a content of data relating to processing that has...
US20100042893 RECONFIGURABLE CYCLIC SHIFTER  
In one embodiment, a reconfigurable cyclic shifter is selectively configurable to operate in (i) five-bit mode to cyclically shift N five-bit messages by up to N degrees or (ii) ten-bit mode to...
US20080040589 PROCESSOR DEVICE  
A processor device having a reservation station (RS) is concerned. In case the processor device has plural RS, the RS is associated with an arithmetic pipeline, and two RS make a pair. When one RS...
US20090077359 ARCHITECTURE RE-UTILIZING COMPUTATIONAL BLOCKS FOR PROCESSING OF HETEROGENEOUS DATA STREAMS  
An architecture for heterogeneous data processing which reuses the same hardware to process different data in different manners is disclosed. The different processing has a substantial similarity;...
US20090204785 Computer with two execution modes  
A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing...
US20090292908 Method and arrangements for multipath instruction processing  
A system is disclosed that includes a fetch stage to retrieve an instruction to be utilized by processing units in a multi-path pipeline. The instruction can have selectors that can select...
US20090240929 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR REDUCED OVERHEAD ADDRESS MODE CHANGE MANAGEMENT IN A PIPELINED, RECYLING MICROPROCESSOR  
A method, system, and computer program product for reduced overhead address mode change management in a pipelined, recycling microprocessor are provided. The recycling microprocessor includes...
US20080313384 Method and Device for Separating the Processing of Program Code in a Computer System Having at Least Two Execution Units  
A method and a device are provided for separating the processing of program code in a computer system having at least two execution units, in which method and device switching over takes place...
US20150006852 FORMING INSTRUCTION GROUPS BASED ON DECODE TIME INSTRUCTION OPTIMIZATION  
Instructions are grouped into instruction groups based on optimizations that may be performed. An instruction is obtained, and a determination is made as to whether the instruction is to be...
US20090070544 Microcontrollers with instruction sets  
A microcontroller includes a plurality of primary registers, a secondary register and a central processing unit (CPU). The primary registers store a plurality of primary data respectively. Each...
US20090259826 Microprocessor Extended Instruction Set Mode  
Disclosed is a system and method of adding functionality to a microprocessor, especially a RISC machine having a plurality of cores, with minimal changes in circuitry and while maintaining legacy...
US20060236079 Unified single-core and multi-mode processor and its program execution method  
A unified single-core and multi-mode processor and its program execution method are provided. In an embodiment of this processor, a single instruction stream is different types of instructions...
US20090271595 Configuring An Application For Execution On A Parallel Computer  
Methods, systems, and products are disclosed for configuring an application for execution on a parallel computer that include: booting up a first subset of a plurality of nodes in a serial...
US20090327670 VARIABLE LENGTH STAGES IN A PIPELINE  
A circuit having a pipeline and a configuration circuit. The pipeline generally has multiple stages linked in series by registers. The registers may be governed by a clock signal having a first...
US20120191952 PROCESSOR IMPLEMENTING SCALAR CODE OPTIMIZATION  
Methods and apparatuses are provided for increased efficiency and enhanced power saving in a processor via scalar code optimization. The method comprises determining that an instruction comprises...
US20060265573 Caching instructions for a multiple-state processor  
A method and apparatus for caching instructions for a processor having multiple operating states. At least two of the operating states of the processor supporting different instruction sets. A...
US20110238963 RECONFIGURABLE ARRAY AND METHOD OF CONTROLLING THE RECONFIGURABLE ARRAY  
A reconfigurable array is provided. The reconfigurable array includes a Very Long Instruction Word (VLIW) mode and a Coarse-Grained Array (CGA) mode. When the VLIW mode is converted to the CGA...
US20110296149 Instruction Set Architecture Extensions for Performing Power Versus Performance Tradeoffs  
Mechanisms are provided for processing an instruction in a processor of a data processing system. The mechanisms operate to receive, in a processor of the data processing system, an instruction,...
US20120084539 METHOD AND SYTEM FOR PREDICATE-CONTROLLED MULTI-FUNCTION INSTRUCTIONS  
Techniques are disclosed for executing conditional computer instructions in an efficient manner that reduces bubbles and idle states. In one embodiment, dual-function instruction execution is...
US20080263340 Method and Device for Analyzing a Signal from a Computer System Having at Least Two Execution Units  
A method and device for analyzing a signal from a computer system having at least two execution units, in the computer system, switchover operations being carried out between at least two...
US20090292907 Dynamic Merging of Pipeline Stages in an Execution Pipeline to Reduce Power Consumption  
A pipelined execution unit incorporates one or more low power modes that reduce power consumption by dynamically merging pipeline stages in an execution pipeline together with one another. In...
US20090037706 Processor Lock  
A data processing system has an embedded processor and a system memory. The embedded processor has access to a specific one of multiple sets of instructions pre-stored in the system memory, only...
US20080288819 Computing System with Transactional Memory Using Millicode Assists  
A computing system processes memory transactions for parallel processing of multiple threads of execution with millicode assists. The computing system transactional memory support provides a...
US20060242389 Job level control of simultaneous multi-threading functionality in a processor  
Using resource sets for job-level control of the simultaneous multi-threading capability (SMT) of a processor in a data processing system. A resource set defined with respect to the processor is...

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