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US20100306512 COMPILER TECHNIQUE FOR EFFICIENT REGISTER CHECKPOINTING TO SUPPORT TRANSACTION ROLL-BACK  
A method and apparatus for efficient register checkpointing is herein described. A transaction is detected in program code. A recovery block is inserted in the program code to perform recovery...
US20130198492 MAJOR BRANCH INSTRUCTIONS  
Major branch instructions are provided that enable execution of a computer program to branch from one segment of code to another segment of code. These instructions also create a new stream of...
US20100332810 Reconfigurable Functional Unit Having Instruction Context Storage Circuitry To Support Speculative Execution of Instructions  
A functional unit is described. The functional unit includes a reconfigurable logic circuitry and instruction context storage circuitry to store instruction context information generated from...
US20110219218 DISTRIBUTED ORDER ORCHESTRATION SYSTEM WITH ROLLBACK CHECKPOINTS FOR ADJUSTING LONG RUNNING ORDER MANAGEMENT FULFILLMENT PROCESSES  
A computer-readable medium, computer-implemented method, and system are provided. In one embodiment, a rollback checkpoint for a step in an executable process is established, and the executable...
US20110066831 SYSTEM AND METHOD FOR SOFTWARE INITIATED CHECKPOINT OPERATIONS  
A method, system and computer program product for issuing one or more software initiated operations for creating a checkpoint of a register file and memory, and for restoring a register file and...
US20140032884 Out-of-Order Checkpoint Reclamation in a Checkpoint Processing and Recovery Core Microarchitecture  
Reclaiming checkpoints in a system in an order that differs from the order when the checkpoints are created. Reclaiming the checkpoints includes: creating one or more checkpoints, each of which...
US20110161639 Event counter checkpointing and restoring  
A method of one aspect may include storing an event count of an event counter that counts events that occur during execution within a logic device. The method may further include restoring the...
US20120079245 DYNAMIC OPTIMIZATION FOR CONDITIONAL COMMIT  
An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During...
US20130046963 ACCESS TO CONTEXT INFORMATION IN A HETEROGENEOUS APPLICATION ENVIRONMENT  
Various embodiments of systems and methods to provide access to context information in a heterogeneous application environment are described herein. The context information of a source application...
US20140189328 POWER REDUCTION BY USING ON-DEMAND RESERVATION STATION SIZE  
A computer processor, a computer system and a corresponding method involve a reservation station that stores instructions which are not ready for execution. The reservation station includes a...
US20110029490 Automatic Checkpointing and Partial Rollback in Software Transaction Memory  
While speculatively executing a given one of a plurality of transactions concurrently executing on a computer, carry out write operations in a local data block, and automatically create an entry...
US20110289303 SETJMP/LONGJMP FOR SPECULATIVE EXECUTION FRAMEWORKS  
A process for check pointing in speculative execution frameworks, identifies calls to a set of setjmp/longjmp instructions to form identified calls to setjmp/longjmp, determines a control flow...
US20130111194 METHOD AND SYSTEM TO PROVIDE USER-LEVEL MULTITHREADING  
A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared...
US20150178091 CONTEXT SAVE AND RESTORE  
Processor context save latency is reduced by only restoring context registers with saved state that differs from the reset value of registers. A system agent monitors access to the design blocks...
US20110154000 Adaptive optimized compare-exchange operation  
A technique to perform a fast compare-exchange operation is disclosed. More specifically, a machine-readable medium, processor, and system are described that implement a fast compare-exchange...
US20100088494 Total cost based checkpoint selection  
A method, system, and computer usable program product for total cost based checkpoint selection are provided in the illustrative embodiments. A cost associated with taking a checkpoint is...
US20120191958 SYSTEM AND METHOD FOR CONTEXT MIGRATION ACROSS CPU THREADS  
One embodiment of the present invention sets forth a technique for associating arbitrary parallel processing unit (PPU) contexts with a given central processing unit (CPU) thread. The technique...
US20130179665 RESTORING A REGISTER RENAMING MAP  
A technique for restoring a register renaming map is described. In one example, a restore table having a number of storage locations saves a copy of the register renaming map whenever a flow-risk...
US20110022869 DEVICE HAVING MULTIPLE INSTRUCTION EXECUTION MODULES AND A MANAGEMENT METHOD  
A multiple instruction execution modules device that comprises a first instruction execution module and a second instruction execution module and a context switch controller; wherein the first...
US20080148026 Checkpoint Efficiency Using a Confidence Indicator  
In one embodiment, a processor comprises a predictor, a checkpoint unit, and circuitry coupled to the checkpoint unit. The predictor is configured to predict an event that can occur during an...
US20130227254 DIFFERENTIAL STACK-BASED SYMMETRIC CO-ROUTINES  
A computing device initiates execution of a first co-routine on the computing device. The first co-routine utilizes an execution stack in a memory of the computing device. A differential symmetric...
US20090043996 USER CO-ROUTINE INTERFACE FOR CUSTOMIZING SIP AND SDP PROTOCOLS  
A method of using co-routines to implement a function-like interface between a BASIC program and the points in the system where SIP and SDP data (for example) are to be modified. This co-routine...
US20090089561 VISUALIZING CHANGES TO CONTENT OVER TIME  
A processing device and method are provided for visualizing changes to dynamic content. Dynamic content may be obtained from a content source and a state of the content may be saved. The saved...
US20080250233 Providing thread fairness in a hyper-threaded microprocessor  
A method and apparatus for providing fairness in a multi-processing element environment is herein described. Mask elements are utilized to associated portions of a reservation station with each...
US20070043934 Early misprediction recovery through periodic checkpoints  
Methods and apparatus to provide misprediction recovery through periodic checkpoint are described. In one embodiment, a renamer unit (e.g., within a processor core) recovers a register alias table...
US20140040595 SPACE EFFICIENT CHECKPOINT FACILITY AND TECHNIQUE FOR PROCESSOR WITH INTEGRALLY INDEXED REGISTER MAPPING AND FREE-LIST ARRAYS  
A processor may efficiently implement register renaming and checkpoint repair even in instruction set architectures with large numbers of wide (bit-width) registers by (i) renaming all destination...
US20080133898 Technique for context state management  
A technique for managing context state information. At least one embodiment includes a plurality of save area segments to store a plurality of machine context state information. One embodiment...
US20060101164 Context switch architecture and system  
A method and system for performing switch operations utilize non-architectural registers to store context information. Data in a first context register on a peripheral system is accessed (e.g.,...
US20070186081 Supporting out-of-order issue in an execute-ahead processor  
One embodiment of the present invention provides a system which supports out-of-order issue in a processor that normally executes instructions in-order. The system starts by issuing instructions...
US20050268073 Critical section availability  
Availability of a critical section is determined according to a state associated with an address table entry and a speculative instruction.
US20140325193 DYNAMIC INSTRUMENTATION  
Techniques for dynamic instrumentation are provided. A method for instrumentation preparation may include obtaining address data of an original instruction in an original instruction stream,...
US20100115249 Support of a Plurality of Graphic Processing Units  
Included are systems and methods for supporting a plurality of Graphics Processing Units (GPUs). At least one embodiment of a system includes a context status register configured to send data...
US20050278513 Systems and methods of dynamic branch prediction in a microprocessor  
A hybrid branch prediction scheme for a multi-stage pipelined microprocessor that combines features of static and dynamic branch prediction to reduce complexity and enhance performance over...
US20090300338 AGGRESSIVE STORE MERGING IN A PROCESSOR THAT SUPPORTS CHECKPOINTING  
Embodiments of the present invention provide a processor that merges stores in an N-entry first-in-first-out (FIFO) store queue. In these embodiments, the processor starts by executing...
US20080155235 Instructions Capable of Preventing Incorrect Usage of UContext Functions in a Multi-Process Environment  
An instruction capable of preventing incorrect usage of ucontext functions in a multi-process environment is disclosed. During an execution of a setcontext instruction, a determination is made...
US20050198475 Thread selection unit and method to fairly allocate processor cycles in a block multithreaded processor  
A thread selection unit for a block multi-threaded processor includes a priority thread selector and an execution thread selector. The priority thread selector uses a maxtime register for each...
US20140095848 Tracking Operand Liveliness Information in a Computer System and Performing Function Based on the Liveliness Information  
Operand liveness state information is maintained during context switches for current architected operands of executing programs the current operand state information indicating whether...
US20060224869 Combination of forwarding/bypass network with history file  
An apparatus, a method, and a processor are provided for recovering the correct state of processor instructions in a processor. This apparatus contains a pipeline of latches, a register file, and...
US20150178077 Instruction and Logic for Non-Blocking Register Reclamation  
A processor includes a logic to execute a first instruction and a second instruction. The first instruction is ordered before the second instruction. Each instruction references a respective...
US20090094444 Link Stack Repair of Erroneous Speculative Update  
Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively...
US20080297669 System and method for Taking Control of a System During a Commercial Break  
During output of a primary media stream from a cable, satellite, television, radio or internet source, a condition, signal or indication of a commercial break is detected causing a context switch...
US20080244246 INTEGRATED MPE-FEC RAM FOR DVB-H RECEIVERS  
A MPE-FEC memory chip and method for use in a DVB-H receiver, wherein the memory chip comprises a TS demux; a RS decoder; a system bus; and a RAM unit adapted to simultaneously interface to the TS...
US20080195849 Cache sharing based thread control  
Apparatus and computing systems associated with cache sharing based thread control are described. One embodiment includes a memory to store a thread control instruction and a processor to execute...
US20150095627 TWO LEVEL RE-ORDER BUFFER  
In response to detecting one or more conditions are met, a checkpoint of a current state of a thread may be created. One or more incomplete instructions may be moved from a first level of a...
US20080244247 Processing long-latency instructions in a pipelined processor  
There is provided a method and processor for processing a thread. The thread comprises a plurality of sequential instructions, the plurality of sequential instructions comprising some...
US20150006864 REGISTER WINDOW PERFORMANCE VIA LAZY REGISTER FILLS  
The present embodiments provide a system that facilitates lazy register window fills in a processor. During program execution, when the system encounters a restore instruction for a register...
US20080162901 Computer Multiple Operation System Switching Method  
The present invention discloses a computer multi-OS switching method, in which a data exchange region for storing OS running environment information is provided, wherein the method comprises: A....
US20090172369 SAVING AND RESTORING ARCHITECTURAL STATE FOR PROCESSOR CORES  
A method and apparatus for saving and restoring architectural states utilizing hardware is herein described. A first portion of an architectural state of a processing element, such as a core, is...
US20090150656 Reducing Aging Effect On Registers  
Methods and apparatus to reduce aging effect on registers are described. In one embodiment, a select value is stored in a register that is unused, for example, to reduce the effects of negative...
US20060225060 Code swapping in embedded DSP systems  
A method for swapping code in a digital signal processor includes determining whether the code is present in an external memory that is external to the digital signal processor or whether the code...

Matches 1 - 50 out of 196 1 2 3 4 >