|
Match
|
Document |
Document Title |
|
|
US20120084538 |
Methodology and Framework for Run-Time Coverage Measurement of Architectural Events of a Microprocessor
A post-silicon testing apparatus, method, and computer program product provide for runtime coverage measurement methodology to measure the architectural events in hardware. Measurement of all...
|
|
|
US20090287907 |
System for providing trace data in a data processor having a pipelined architecture
The invention is a method and system for providing trace data in a pipelined data processor. Aspects of the invention include providing a trace pipeline in parallel to the execution pipeline,...
|
|
|
US20090217012 |
MICROARCHITECTURE, METHOD AND COMPUTER PROGRAM PRODUCT FOR EFFICIENT DATA GATHERING FROM A SET OF TRACE ARRAYS
An architecture for collecting performance data in a processor, that includes: a trace read control unit and a trace data collect unit, each unit coupled to a plurality of trace array and multiplex...
|
|
|
US20110154121 |
CONCURRENCY TEST EFFICTIVENESS VIA MUTATION TESTING AND DYNAMIC LOCK ELISION
One embodiment described herein is directed to a method practiced in a computing environment. The method includes acts for determining test suite effectiveness for testing for concurrency problems...
|
|
|
US20090217010 |
DATA PROCESSOR DEVICE HAVING TRACE CAPABILITIES AND METHOD
In response to determining an event has occurred, information is stored at a trace buffer of an integrated circuit. When the trace buffer is full, execution of instructions at a CPU is halted to...
|
|
|
US20050223364 |
Method and apparatus to compact trace in a trace buffer
A method and apparatus to compact trace in a trace buffer are described.
|
|
|
US20090249045 |
APPARATUS AND METHOD FOR CONDENSING TRACE INFORMATION IN A MULTI-PROCESSOR SYSTEM
A computer readable storage medium includes executable instructions to characterize a coherency controller. The executable instructions define ports to receive processor trace information from a...
|
|
|
US20090265530 |
Latency hiding of traces using block coloring
An embodiment of the present invention is a technique to hide latency in program traces. Blocks of instructions between start and end of a critical section are associated with color information....
|
|
|
US20110119651 |
TECHNIQUES RELATED TO CUSTOMIZATIONS FOR COMPOSITE APPLICATIONS
A framework is provided for enabling and managing customizations to an application. In one embodiment, techniques are provided that enable the customizability of an application to be controlled...
|
|
|
US20110138359 |
MODIFIED IMPLEMENTATION OF JAVA DEBUG WIRE PROTOCOL
A client debugger application or a virtual machine includes a receiving module configured to receive a command packet of a debugging protocol from a computer. The command packet includes an...
|
|
|
US20110225400 |
Device for Testing a Multitasking Computation Architecture and Corresponding Test Method
A device and method for testing a multitasking computation architecture is provided. Sequences of test instructions are generated corresponding to programming rules for the computation...
|
|
|
US20110320783 |
VERIFICATION USING OPCODE COMPARE
A verification method is provided and includes randomly choosing a hardware executed instruction in a predefined program to force Opcode Compare on, determining an identity of a corresponding...
|
|
|
US20070283133 |
Reducing bandwidth required for trace data
A data processing apparatus is disclosed comprising: trace logic for monitoring behaviour of a portion of said data processing apparatus; and prediction logic operable to provide at least one...
|
|
|
US20110078421 |
ENHANCED MONITOR FACILITY
A monitoring facility that is operable in two modes allowing compatibility with prior existing monitoring facilities. In one mode, in response to encountering a monitored event, an interrupt is...
|
|
|
US20110219217 |
System on Chip Breakpoint Methodology
A system-on-chip (SoC) with a debugging methodology. The system-on-chip (SoC) includes a central processing unit (CPU) and multiple computing elements connected to the CPU. The CPU is configured to...
|
|
|
US20060294343 |
Realtime compression of microprocessor execution history
A trace compression unit is included in a processor system that has a processor core and an external system memory. The trace compression unit encrypts the processor core execution history into...
|
|
|
US20090276610 |
TEST CASE GENERATION WITH BACKWARD PROPAGATION OF PREDEFINED RESULTS AND OPERAND DEPENDENCIES
A method of generating a test case from a given test case structure, the method including generating instructions for the given test case structure, propagating predefined results in a backwards...
|
|
|
US20090300427 |
METHOD OF LOGGING STACK TRACE INFORMATION
A computer system comprises a memory configured to store software instructions; a set of registers; and a processing unit configured to temporarily store passed parameters in the set of registers...
|
|
|
US20080082802 |
Microcomputer debugging system
A microcomputer debugging system capable of executing a plurality of debug modes, wherein processing is not allowed to shift to an interruption program during a debugging operation in one of the...
|
|
|
US20090313460 |
TRACE COMPRESSION METHOD FOR DEBUG AND TRACE INTERFACE OF MICROPROCESSOR
The present invention proposed a trace compression method for a debug and trace interface of a microprocessor, in which the debug and trace interface is associated with a plurality of registers for...
|
|
|
US20060031662 |
Processor implementing conditional execution and including a serial queue
A processor is disclosed including trace and profile logic for gathering and producing data corresponding to events occurring during instruction execution. In one embodiment, the trace and profile...
|
|
|
US20080184014 |
METHOD FOR EFFICIENTLY EMULATING COMPUTER ARCHITECTURE CONDITION CODE SETTINGS
Emulation of source machine instructions is provided in which target machine CPU condition codes are employed to produce emulated condition code settings without the use, encoding or generation of...
|
|
|
US20090187747 |
SYSTEM AND METHOD FOR TRACING INSTRUCTION POINTERS AND DATA ACCESS
A system and method for tracing instruction pointers and data access is disclosed. In one embodiment the system includes a plurality of trace units including at least one first trace unit...
|
|
|
US20080046699 |
Method and apparatus for non-deterministic incremental program replay using checkpoints and syndrome tracking
Methods and apparatus are provided for non-deterministic incremental program replay using checkpoints and syndrome tracking. Replay of a program proceeds by, for a given execution of the program,...
|
|
|
US20060259750 |
SELECTIVELY EMBEDDING EVENT-GENERATING INSTRUCTIONS
An information carrier medium containing debugging software that, when executed by a processor, causes the processor to receive information from hardware in communication with the processor, the...
|
|
|
US20050188186 |
Obtaining execution path information in an instruction sampling system
A method of linking control transfer information with sampling information for instructions executing in a processor which includes storing information relating to execution events, selecting an...
|
|
|
US20100251160 |
MEASUREMENT AND REPORTING OF PERFORMANCE EVENT RATES
Methods and systems are disclosed for measuring performance event rates at a computer and reporting the performance event rates using timelines. A particular method tracks, for a time period, the...
|
|
|
US20080263338 |
EXCEPTION OPERATION APPARATUS, METHOD AND COMPUTER PROGRAM FOR CONTROLLING DEBUGGING APPARATUS, AND TELEVISION AND CELLULAR PHONE PROVIDING THE SAME
In order to automatically activate a debugger while maintaining the status of the machine as it was just before execution of the instruction which has raised an exception even in a case in which a...
|
|
|
US20070050607 |
Alteration of execution of a program in response to an execution-optimization information
Embodiments include a device, and a method. In an embodiment, a device includes an information store operable to save an execution-optimization information, a first processor, and a hardware...
|
|
|
US20110131396 |
TIMING ANALYSIS
One aspect of the present invention provides processor comprising: an execution unit arranged to execute a sequence of instructions each comprising a respective opcode; and a counter coupled to the...
|
|
|
US20090307468 |
Generating a Test Case Micro Generator During Processor Design Verification and Validation
A main generator generates a micro generator and initial test cases based upon a processor architecture specifications and user input, such as general purpose register availability, translation...
|
|
|
US20070288728 |
CPU utilization metering on sytems that include multiple hardware threads per core
Indicating usage in a system is disclosed. Indicating includes obtaining active thread information related to a number of hardware threads in a processor core, combining the active thread...
|
|
|
US20100017583 |
Call Stack Sampling for a Multi-Processor System
A computer implemented method, apparatus, and computer usable program code for sampling call stack information. Responsive to identifying an interrupt, a determination is made as to whether all...
|
|
|
US20110219216 |
Mechanism for Performing Instruction Scheduling based on Register Pressure Sensitivity
A mechanism for performing instruction scheduling based on register pressure sensitivity is disclosed. A method of embodiments of the invention includes performing a preliminary register pressure...
|
|
|
US20070005944 |
Opportunistic transmission of computing system state information within a link based computing system
A method is described that involves within a link based computing system, opportunistically transmitting, into a network utilized by components of the link based computing system, one or more...
|
|
|
US20090077357 |
Method of Power Simulation and Power Simulator
Disclosed are a method of simulating power and a power simulator. The power simulator includes a static information extracting unit that extracts static information with respect to execution of the...
|
|
|
US20090249046 |
APPARATUS AND METHOD FOR LOW OVERHEAD CORRELATION OF MULTI-PROCESSOR TRACE INFORMATION
A method of coordinating trace information in a multiprocessor system includes receiving processor trace information from a set of processors. The processor trace information from each processor...
|
|
|
US20120089820 |
HYBRID MECHANISM FOR MORE EFFICIENT EMULATION AND METHOD THEREFOR
In a host system, a method for using instruction scheduling to efficiently emulate the operation of a target computing syste includes preparing, on the host system, an instruction sequence to...
|
|
|
US20050198555 |
Incorporating instruction reissue in an instruction sampling mechanism
A method of sampling instructions executing in a processor which includes selecting an instruction for sampling, gathering sampling information for the instruction, determining whether the...
|
|
|
US20080126768 |
Method and apparatus for aiding verification of circuit, and computer product
A verification aiding apparatus includes an acquiring unit that acquires implementation description information of a verification target circuit, and a classifying unit that classifies registers in...
|
|
|
US20100023736 |
RECONFIGURABLE CIRCUIT, RESET METHOD, AND CONFIGURATION INFORMATION GENERATION DEVICE
The present invention provides a reconfigurable circuit that comprises a plurality of reconfiguration cells and changes a configuration of a computation processing unit included in each of the...
|
|
|
US20080288753 |
Methods and Apparatus for Emulating the Branch Prediction Behavior of an Explicit Subroutine Call
An apparatus for emulating the branch prediction behavior of an explicit subroutine call is disclosed. The apparatus includes a first input which is configured to receive an instruction address and...
|
|
|
US20100325401 |
Method of Translating N to N Instructions Employing an Enhanced Extended Translation Facility
A method, article, and system for providing an effective implementation of assembler language translate-n-to-n instructions implemented on 21, 31, and 64-bit architectures, while maintaining...
|
|
|
US20070050609 |
Cross-architecture execution optimization
Embodiments include a device, apparatus, and a method. A device includes an input circuit for receiving data corresponding to a runtime execution of a first instruction by a first processor having...
|
|
|
US20080215862 |
Program Creation Device, Program Test Device, Program Execution Device, Information Processing System
The present invention comprises a program generation apparatus for generating an obfuscated program difficult to analyze from outside and a program execution apparatus for executing the program....
|
|
|
US20080114971 |
BRANCH HISTORY TABLE FOR DEBUG
A computer implemented method, apparatus, and computer program product for preserving branch history data. The process creates a branch history table in a buffer. The process saves an address for...
|
|
|
US20090300420 |
Method for Testing at Least One Arithmetic Unit Installed in a Control Unit
A method for testing at least two arithmetic units installed in a control unit includes: loading of first test data for testing a first arithmetic unit; saving the loaded first test data in a...
|
|
|
US20100138639 |
SANDBOXED EXECUTION OF PLUG-INS
A sandbox architecture that isolates and identifies misbehaving plug-ins (intentional or unintentional) to prevent system interruptions and failure. Based on plug-in errors, the architecture...
|
|
|
US20050033945 |
Dynamically changing the semantic of an instruction
A technique comprises receiving an instruction and dynamically changing the instruction's semantic based on programmable information that is separate from the instruction. The change in semantic...
|
|
|
US20090055632 |
Emulation Scheme for Programmable Pipeline Fabric
The present invention allows emulation of a programmable pipeline processor fabric or architecture. According to certain aspects, the invention permits real-time capture of state information for...
|