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Match Document Document Title
US20100005316 BRANCH TRACE METHODOLOGY  
Method, system, and computer program product embodiments for performing a branch trace operation on a computer system of an end user are provided. An encrypted mapping macro is provided to the end...
US20140189324 PHYSICAL REGISTER TABLE FOR ELIMINATING MOVE INSTRUCTIONS  
Embodiments of an invention for a physical register table for eliminating move instructions are disclosed. In one embodiment, a processor includes a physical register file, a register allocation...
US20140189325 PAGING IN SECURE ENCLAVES  
Embodiments of an invention for paging in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a...
US20110099357 Utilizing a Bidding Model in a Microparallel Processor Architecture to Allocate Additional Registers and Execution Units for Short to Intermediate Stretches of Code Identified as Opportunities for Microparallelization  
An enhanced mechanism for parallel execution of computer programs utilizes a bidding model to allocate additional registers and execution units for stretches of code identified as opportunities...
US20130111192 Adjusting acknowledgement requests for remote control transmissions based on previous acknowledgements  
A remote receives an instruction to transmit and determines whether or not to include an acknowledgement request in the instruction based on statistics regarding receipt of acknowledgements...
US20130318330 PREDICTING AND AVOIDING OPERAND-STORE-COMPARE HAZARDS IN OUT-OF-ORDER MICROPROCESSORS  
A method and information processing system manage load and store operations that can be executed out-of-order. At least one of a load instruction and a store instruction is executed. A...
US20110153986 PREDICTING AND AVOIDING OPERAND-STORE-COMPARE HAZARDS IN OUT-OF-ORDER MICROPROCESSORS  
A method and information processing system manage load and store operations executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made...
US20140181482 STORE-TO-LOAD FORWARDING  
An arithmetic unit performs store-to-load forwarding based on predicted dependencies between store instructions and load instructions. In some embodiments, the arithmetic unit maintains a table of...
US20120005530 System and Method for Communication Between Concurrent Transactions Using Transaction Communicator Objects  
Transactional memory implementations may be extended to include special transaction communicator objects through which concurrent transactions can communicate. Changes by a first transaction to a...
US20150113254 EFFICIENCY THROUGH A DISTRIBUTED INSTRUCTION SET ARCHITECTURE  
A subsystem is configured to support a distributed instruction set architecture with primary and secondary execution pipelines. The primary execution pipeline supports the execution of a subset of...
US20130138930 COMPUTER SYSTEMS AND METHODS FOR REGISTER-BASED MESSAGE PASSING  
Systems and methods are disclosed that include a plurality of processing units having a plurality of register file entries. Control logic identifies a first register entry as including a message...
US20130283017 HARD OBJECT: CONSTRAINING CONTROL FLOW AND PROVIDING LIGHTWEIGHT KERNEL CROSSINGS  
A method providing simple fine-grain hardware primitives with which software engineers can efficiently implement enforceable separation of programs into modules and constraints on control flow,...
US20140244984 ELIGIBLE STORE MAPS FOR STORE-TO-LOAD FORWARDING  
The present invention provides a method and apparatus for generating eligible store maps for store-to-load forwarding. Some embodiments of the method include generating information associated with...
US20130173892 CONVERT TO ZONED FORMAT FROM DECIMAL FLOATING POINT FORMAT  
Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from...
US20130339680 NONTRANSACTIONAL STORE INSTRUCTION  
A NONTRANSACTIONAL STORE instruction, executed in transactional execution mode, performs stores that are retained, even if a transaction associated with the instruction aborts. The stores include...
US20120198213 PACKET HANDLER INCLUDING PLURALITY OF PARALLEL ACTION MACHINES  
A packet handler for a packet processing system includes a plurality of parallel action machines, each of the plurality of parallel action machines being configured to perform a respective packet...
US20120317402 EXECUTING A START OPERATOR MESSAGE COMMAND  
A facility is provided to enable operator message commands from multiple, distinct sources to be provided to a coupling facility of a computing environment for processing. These commands are used,...
US20110145551 TWO-STAGE COMMIT (TSC) REGION FOR DYNAMIC BINARY OPTIMIZATION IN X86  
Generally, the present disclosure provides systems and methods to generate a two-stage commit (TSC) region which has two separate commit stages. Frequently executed code may be identified and...
US20110087865 Intermediate Register Mapper  
A method, processor, and computer program product employing an intermediate register mapper within a register renaming mechanism. A logical register lookup determines whether a hit to a logical...
US20140059329 ALLOCATION OF COUNTERS FROM A POOL OF COUNTERS TO TRACK MAPPINGS OF LOGICAL REGISTERS TO PHYSICAL REGISTERS FOR MAPPER BASED INSTRUCTION EXECUTIONS  
A computer system assigns a particular counter from among a plurality of counters currently in a counter free pool to count a number of mappings of logical registers from among a plurality of...
US20150039867 INSTRUCTION SOURCE SPECIFICATION  
Techniques are disclosed relating to specification of instruction operands. In some embodiments, this may involve assigning operands to source inputs. In one embodiment, an instruction includes...
US20080256336 MICROPROCESSOR WITH PRIVATE MICROCODE RAM  
A microprocessor includes a private RAM (PRAM), for use by microcode, which is non-user-accessible and within its own distinct address space from the system memory address space. The PRAM is...
US20120030452 MODIFYING COMMANDS  
The present disclosure includes methods, devices, modules, and systems for modifying commands. One device embodiment includes a memory controller including a channel, wherein the channel includes...
US20110107068 ELIMINATING REDUNDANT OPERATIONS FOR COMMON PROPERTIES USING SHARED REAL REGISTERS  
One embodiment of a method for eliminating redundant operations establishing common properties includes identifying a first virtual register storing a first value having a common property. The...
US20090193235 TRANSFER SYSTEM, AND TRANSFER METHOD  
In response to a transfer request, for which a loading time at a transfer source and a loading time at a transfer target are designated by a production controller, there is created a transfer...
US20120265971 ALLOCATION OF COUNTERS FROM A POOL OF COUNTERS TO TRACK MAPPINGS OF LOGICAL REGISTERS TO PHYSICAL REGISTERS FOR MAPPER BASED INSTRUCTION EXECUTIONS  
A mapper unit of an out-of-order processor assigns a particular counter currently in a counter free pool to count a number of mappings of logical registers to a particular physical register from...
US20080301416 SYSTEM AND PROGRAM PRODUCT OF DOING PACK UNICODE Z SERIES INSTRUCTIONS  
Emulation methods are provided for two PACK instructions, one for Unicode data and the other for ASCII coded data in which processing is carried out in a block-by-block fashion as opposed to a...
US20140164744 Tracking Multiple Conditions in a General Purpose Register and Instruction Therefor  
An operate-and-insert instruction of a program, when executed performs an operation based on one or more operands, results of an instruction specified test of the operation performed are stored in...
US20130117546 Load Pair Disjoint Facility and Instruction Therefore  
A Load/Store Disjoint instruction, when executed by a CPU, accesses operands from two disjoint memory locations and sets condition code indicators to indicate whether or not the two operands...
US20110202748 LOAD PAIR DISJOINT FACILITY AND INSTRUCTION THEREFORE  
A Load/Store Disjoint instruction, when executed by a CPU, accesses operands from two disjoint memory locations and sets condition code indicators to indicate whether or not the two operands...
US20090094442 Storage medium storing load detecting program and load detecting apparatus  
A load detecting apparatus includes a load controller, and judges a motion of a player on the basis of detected load values. Judgment timing for a motion of putting the feet on and down from the...
US20050251660 Method and system for specualtively sending processor-issued store operations to a store queue with full signal asserted  
A method and processor chip design for enabling a processor core to continue sending store operations speculatively to the store queue after the core receives indication that the store queue is...
US20090037701 Method of Updating Electronic Operationg Instructions of a Vehicle and an Operating Instructions Updating System  
A method and system for updating electronic operating instructions of a vehicle is provided. Local operating instruction data objects are stored in a local storage device arranged in the vehicle...
US20150121045 READING A REGISTER PAIR BY WRITING A WIDE REGISTER  
A read operation is initiated to obtain a wide input operand. Based on the initiating, a determination is made as to whether the wide input operand is available in a wide register or in two narrow...
US20150106599 EXECUTION OF A PERFORM FRAME MANAGEMENT FUNCTION INSTRUCTION  
Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host...
US20090172365 Instructions and logic to perform mask load and store operations  
In one embodiment, logic is provided to receive and execute a mask move instruction to transfer a vector data element including a plurality of packed data elements from a source location to a...
US20140122840 EFFICIENT USAGE OF A MULTI-LEVEL REGISTER FILE UTILIZING A REGISTER FILE BYPASS  
A processor includes an execution unit, a first level register file, a second level register file, a plurality of storage locations and a register file bypass controller. The first and second...
US20120260075 CONDITIONAL ALU INSTRUCTION PRE-SHIFT-GENERATED CARRY FLAG PROPAGATION BETWEEN MICROINSTRUCTIONS IN READ-PORT LIMITED REGISTER FILE MICROPROCESSOR  
A microprocessor includes a hardware instruction translator that translates an architectural instruction into first and second microinstructions. To execute the first microinstruction, an...
US20080313439 PIPELINE DEVICE WITH A PLURALITY OF PIPELINED PROCESSING UNITS  
In a pipeline device, the output of each of processing units is connected to a corresponding one of data output lines of data transfer lines. Input selectors are provided for the processing units,...
US20140122841 EFFICIENT USAGE OF A REGISTER FILE MAPPER AND FIRST-LEVEL DATA REGISTER FILE  
A processor includes a first level register file, second level register file, and register file mapper. The first and second level register files are comprised of physical registers, with the...
US20120331276 Instruction Execution  
A method of executing an instruction set to select a set of registers, includes reading a first instruction of the instruction set; interpreting a first operand of the first instruction to...
US20140223149 METHOD OF ENTROPY RANDOMIZATION ON A PARALLEL COMPUTER  
Method, system, and computer program product for randomizing entropy on a parallel computing system using network arithmetic logic units (ALUs). In one embodiment, network ALUs on nodes of the...
US20140223148 METHOD OF ENTROPY RANDOMIZATION ON A PARALLEL COMPUTER  
Method, system, and computer program product for randomizing entropy on a parallel computing system using network arithmetic logic units (ALUs). In one embodiment, network ALUs on nodes of the...
US20140189326 MEMORY MANAGEMENT IN SECURE ENCLAVES  
Embodiments of an invention for memory management in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to...
US20080189525 IMPLEMENTING A TWO PHASE OPEN FIRMWARE DRIVER IN ADAPTER FCODE  
A computer implemented method, data processing system, and computer usable program code are provided for implementing a two phase open firmware driver. A computer system probes a device for a...
US20080222400 Power Consumption of a Microprocessor Employing Speculative Performance Counting  
Reduction of power consumption and chip area of a microprocessor employing speculative performance counting, comprising splitting a counter and a backup register of a speculative counting...
US20140229718 SPECULATIVE LOAD ISSUE  
A method and load and store buffer for issuing a load instruction to a data cache. The method includes determining whether there are any unresolved store instructions in the store buffer that are...
US20080140994 Data-Parallel processing unit  
A method of operation within an integrated-circuit processing device having a plurality of execution lanes. Upon receiving an instruction to exchange data between the execution lanes, respective...
US20140122842 EFFICIENT USAGE OF A REGISTER FILE MAPPER MAPPING STRUCTURE  
A processor with a register file mapper can use a hasher to improve the distribution of mappings within a mapping structure. The hasher generates a value based, at least in part, on a thread...
US20080244243 Computer program product and system for altering execution flow of a computer program  
A debugger alters the execution flow of a child computer program of the debugger at runtime by inserting jump statements determined by the insertion of breakpoint instructions. Breakpoints are...

Matches 1 - 50 out of 382 1 2 3 4 5 6 7 8 >