Matches 1 - 50 out of 219 1 2 3 4 5 >

AcclaimIP-ad

Match Document Document Title
US20130036296 FLOATING POINT EXECUTION UNIT WITH FIXED POINT FUNCTIONALITY  
A floating point execution unit is capable of selectively repurposing one or more adders in an exponent path of the floating point execution unit to perform fixed point addition operations,...
US20140237217 VECTORIZATION IN AN OPTIMIZING COMPILER  
An optimizing compiler includes a vectorization mechanism that optimizes a computer program by substituting code that includes one or more vector instructions (vectorized code) for one or more...
US20110314251 MEMORY SAFETY OF FLOATING-POINT COMPUTATIONS  
Concepts and technologies are described herein for determining memory safety of floating-point computations. The concepts and technologies described herein analyze code to determine if any...
US20140281419 COMBINED FLOATING POINT MULTIPLIER ADDER WITH INTERMEDIATE ROUNDING LOGIC  
An error handling method includes identifying a code region eligible for cumulative multiply add (CMA) optimization and translating code region instructions into interpreter code instructions,...
US20130067204 Instructions With Floating Point Control Override  
Methods and apparatus relating to instructions with floating point control override are described. In an embodiment, floating point operation settings indicated by a floating point control...
US20150052335 INTERPOLATION IMPLEMENTATION  
Techniques are disclosed relating to floating-point operations in computer processors. In one embodiment, an apparatus includes a floating-point unit and circuitry configured to receive an initial...
US20120290819 DSP BLOCK WITH EMBEDDED FLOATING POINT STRUCTURES  
A specialized processing block includes a first floating-point arithmetic operator stage, a second floating-point arithmetic operator stage, and configurable interconnect within the specialized...
US20110208505 ASSIGNING FLOATING-POINT OPERATIONS TO A FLOATING-POINT UNIT AND AN ARITHMETIC LOGIC UNIT  
A processor may include a floating-point unit (FPU) and an arithmetic logic unit (ALU). Instructions to the processor may include greater or lesser amounts of floating-point operations and integer...
US20110173421 MULTI-INPUT AND BINARY REPRODUCIBLE, HIGH BANDWIDTH FLOATING POINT ADDER IN A COLLECTIVE NETWORK  
To add floating point numbers in a parallel computing system, a collective logic device receives the floating point numbers from computing nodes. The collective logic devices converts the floating...
US20140149720 FLOATING POINT EXECUTION UNIT FOR CALCULATING PACKED SUM OF ABSOLUTE DIFFERENCES  
A method and circuit arrangement provide support for packed sum of absolute difference operations in a floating point execution unit, e.g., a scalar or vector floating point execution unit....
US20150006859 MULTIFUNCTIONAL HEXADECIMAL INSTRUCTION FORM SYSTEM AND PROGRAM PRODUCT  
A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the...
US20130191619 MULTIFUNCTION HEXADECIMAL INSTRUCTION FORM SYSTEM AND PROGRAM PRODUCT  
A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the...
US20110060892 SPECULATIVE FORWARDING OF NON-ARCHITECTED DATA FORMAT FLOATING POINT RESULTS  
A microprocessor having an instruction set architecture (ISA) that specifies at least one architected data format (ADF) for floating-point operands includes first and second floating-point units....
US20120151191 REDUCING POWER CONSUMPTION IN MULTI-PRECISION FLOATING POINT MULTIPLIERS  
Methods and apparatus relating to reducing power consumption in multi-precision floating point multipliers are described. In an embodiment, certain portions of a multiplier are disabled in...
US20110047359 Insertion of Operation-and-Indicate Instructions for Optimized SIMD Code  
Mechanisms are provided for inserting indicated instructions for tracking and indicating exceptions in the execution of vectorized code. A portion of first code is received for compilation. The...
US20140317387 METHOD FOR PERFORMING DUAL DISPATCH OF BLOCKS AND HALF BLOCKS  
A method for executing dual dispatch of blocks and half blocks. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form...
US20140089644 CIRCUIT AND METHOD FOR IDENTIFYING EXCEPTION CASES IN A FLOATING-POINT UNIT AND GRAPHICS PROCESSING UNIT EMPLOYING THE SAME  
A floating-point unit and a method of identifying exception cases in a floating-point unit. In one embodiment, the floating-point unit includes: (1) a floating-point computation circuit having a...
US20140344555 Scalable Partial Vectorization  
A system, method and computer program product to compute latencies of a plurality of expression trees in a basic block and to select a first and a second expression tree from the plurality of...
US20140229716 VECTOR AND SCALAR BASED MODULAR EXPONENTIATION  
An embodiment includes a method for computing operations, such as modular exponentiation, using a mix of vector and scalar instructions to accelerate various applications such as encryption...
US20110004644 DYNAMIC FLOATING POINT REGISTER PRECISION CONTROL  
Apparatus and methods are provided to perform floating point operations that are adaptive to the precision formats of input operands. The apparatus includes adaptive conversion logic and a tagged...
US20150039866 COMPUTER FOR AMDAHL-COMPLIANT ALGORITHMS LIKE MATRIX INVERSION  
A family of computers is disclosed and claimed that supports simultaneous processes from the single core up to multi-chip Program Execution Systems (PES). The instruction processing of the...
US20080263335 Representation of Modal Intervals within a Computer  
A modal interval representation having improved computational utility is provided. The modal interval representation generally includes a binary quantifier, and a set theoretical interval for...
US20110161624 Floating Point Collect and Operate  
Mechanisms are provided for performing a floating point collect and operate for a summation across a vector for a dot product operation. A routing network placed before the single instruction...
US20140351564 SIMPLIFICATION OF LARGE NETWORKS AND GRAPHS  
Embodiments relate to simplifying large and complex networks and graphs using global connectivity information based on calculated node centralities. An aspect includes calculating node...
US20130073836 FINE-GRAINED INSTRUCTION ENABLEMENT AT SUB-FUNCTION GRANULARITY  
Fine-grained enablement at sub-function granularity. An instruction encapsulates different sub-functions of a function, in which the sub-functions use different sets of registers of a composite...
US20120011348 Matrix Multiplication Operations Using Pair-Wise Load and Splat Operations  
Mechanisms for performing a matrix multiplication operation are provided. A vector load operation is performed to load a first vector operand of the matrix multiplication operation to a first...
US20150089206 CONVERT TO ZONED FORMAT FROM DECIMAL FLOATING POINT FORMAT  
Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from...
US20150089205 CONVERT FROM ZONED FORMAT TO DECIMAL FLOATING POINT FORMAT  
Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from...
US20130173891 CONVERT FROM ZONED FORMAT TO DECIMAL FLOATING POINT FORMAT  
Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from...
US20110029760 NON-ATOMIC SCHEDULING OF MICRO-OPERATIONS TO PERFORM ROUND INSTRUCTION  
A microprocessor executes an instruction specifying a floating-point input operand having a predetermined size and that instructs the microprocessor to round the floating-point input operand to an...
US20100274993 LOGICAL MAP TABLE FOR DETECTING DEPENDENCY CONDITIONS  
Techniques and structures are described which allow the detection of certain dependency conditions, including evil twin conditions, during the execution of computer instructions. Information used...
US20150052336 SELECTIVELY CONTROLLING INSTRUCTION EXECUTION IN TRANSACTIONAL PROCESSING  
Execution of instructions in a transactional environment is selectively controlled. A TRANSACTION BEGIN instruction initiates a transaction and includes controls that selectively indicate whether...
US20130103932 MULTI-ADDRESSABLE REGISTER FILES AND FORMAT CONVERSIONS ASSOCIATED THEREWITH  
A multi-addressable register file is addressed by a plurality of types of instructions, including scalar, vector and vector-scalar extension instructions. It may be determined that data is to be...
US20110296146 HARDWARE INSTRUCTIONS TO ACCELERATE TABLE-DRIVEN MATHEMATICAL FUNCTION EVALUATION  
A set of instructions for implementation in a floating-point unit or other computer processor hardware is disclosed herein. In one embodiment, an extended-range fused multiply-add operation, a...
US20100100713 FAST FLOATING POINT COMPARE WITH SLOWER BACKUP FOR CORNER CASES  
A floating point processor unit executes a floating point compare instruction with two operands of the same or different precision by comparing the two operands in integer format, which speeds up...
US20150121043 COMPUTER AND METHODS FOR SOLVING MATH FUNCTIONS  
Computers and methods for performing mathematical functions are disclosed. An embodiment of a computer includes an operations level and a driver level. The operations level performs mathematical...
US20140208078 VECTOR CHECKSUM INSTRUCTION  
A Vector Checksum instruction. Elements from a second operand are added together one-by-one to obtain a first result. The adding includes performing one or more end around carry add operations....
US20130159681 VERIFYING SPECULATIVE MULTITHREADING IN AN APPLICATION  
Verifying speculative multithreading in an application executing in a computing system, including: executing one or more test instructions serially thereby producing a serial result, including...
US20140052969 SUPER MULTIPLY ADD (SUPER MADD) INSTRUCTIONS WITH THREE SCALAR TERMS  
A processing core is described having execution unit logic circuitry having a first register to store a first vector input operand, a second register to a store a second vector input operand and a...
US20100318772 SUPERSCALAR REGISTER-RENAMING FOR A STACK-ADDRESSED ARCHITECTURE  
A system and method for increasing processor throughput by decreasing a loop critical path. In one embodiment, a table comprises multiple stack entries, each comprising an x87 floating-point (FP)...
US20100042816 BREAK, PRE-BREAK, AND REMAINING INSTRUCTIONS FOR PROCESSING VECTORS  
The described embodiments provide a system that sets elements in a result vector based on an input vector. During operation, the system determines a location of a key element within the input...
US20120079253 FUNCTIONAL UNIT FOR VECTOR LEADING ZEROES, VECTOR TRAILING ZEROES, VECTOR OPERAND 1s COUNT AND VECTOR PARITY CALCULATION  
A method of performing vector operations on a semiconductor chip is described. The method includes performing a first vector instruction with a vector functional unit implemented on the...
US20090138678 Multifunction Hexadecimal Instruction Form System and Program Product  
A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the...
US20080133895 Floating Point Addition  
Methods and apparatus to perform floating point addition are described. In one embodiment, a plurality of operands are formatted into a common format and combined (e.g., added or subtracted)....
US20110138155 VECTOR COMPUTER AND INSTRUCTION CONTROL METHOD THEREFOR  
A vector computer executing vector operations via vector pipeline processing is restructured to dynamically perform an overtaking control on vector gather/scatter instructions. Minimum/maximum...
US20130179661 Performing A Multiply-Multiply-Accumulate Instruction  
In one embodiment, the present invention includes a processor having multiple execution units, at least one of which includes a circuit having a multiply-accumulate (MAC) unit including multiple...
US20120079252 PERFORMING A MULTIPLY-MULTIPLY-ACCUMULATE INSTRUCTION  
In one embodiment, the present invention includes a processor having multiple execution units, at least one of which includes a circuit having a multiply-accumulate (MAC) unit including multiple...
US20130073837 Input Vector Analysis for Memoization Estimation  
A function's purity may be estimated by comparing a new input vector to previously analyzed input vectors. When a new input vector is within a confidence boundary, the new input vector may be...
US20140289502 ENHANCED VECTOR TRUE/FALSE PREDICATE-GENERATING INSTRUCTIONS  
Systems, apparatuses and methods for utilizing enhanced vector true/false instructions. The enhanced vector true/false instructions generate enhanced predicates to correspond to the request...
US20140059328 MECHANISM FOR PERFORMING SPECULATIVE PREDICATED INSTRUCTIONS  
A mechanism for executing speculative predicated instructions may include execution of initiating execution of a vector instruction when one or more operands upon which the vector instruction...
Matches 1 - 50 out of 219 1 2 3 4 5 >