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US20140281415 DYNAMIC RENAME BASED REGISTER RECONFIGURATION OF A VECTOR REGISTER FILE  
Reconfiguring a register file using a rename table having a plurality of fields that indicate fracture information about a source register of an instruction for instructions which have narrow to...
US20130151819 RECOVERING FROM EXCEPTIONS AND TIMING ERRORS  
A data processing apparatus with a processing pipeline, the pipeline including exception control circuitry and error detection circuitry. An exception storage unit is configured to maintain an...
US20100306509 OUT-OF-ORDER EXECUTION MICROPROCESSOR WITH REDUCED STORE COLLISION LOAD REPLAY REDUCTION  
An out-of-order execution microprocessor for reducing the likelihood of having to replay a load instruction due to a store collision. The microprocessor includes a queue of entries, each entry...
US20140047218 MULTI-STAGE REGISTER RENAMING USING DEPENDENCY REMOVAL  
Multi-stage register renaming using dependency removal is described. In an embodiment, the registers are renamed in two stages. The first stage involves removing all the dependencies within a set...
US20150089201 ROTATE INSTRUCTIONS THAT COMPLETE EXECUTION EITHER WITHOUT WRITING OR READING FLAGS  
A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand...
US20150089200 ROTATE INSTRUCTIONS THAT COMPLETE EXECUTION EITHER WITHOUT WRITING OR READING FLAGS  
A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand...
US20150089199 ROTATE INSTRUCTIONS THAT COMPLETE EXECUTION EITHER WITHOUT WRITING OR READING FLAGS  
A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand...
US20140122837 NOVEL REGISTER RENAMING SYSTEM USING MULTI-BANK PHYSICAL REGISTER MAPPING TABLE AND METHOD THEREOF  
Embodiments of a processor architecture utilizing multi-bank implementation of physical register mapping table are provided. A register renaming system to correlate architectural registers to...
US20140344554 MICROPROCESSOR ACCELERATED CODE OPTIMIZER AND DEPENDENCY REORDERING METHOD  
A dependency reordering method. The method includes accessing an input sequence of instructions, initializing three registers, and loading instruction numbers into a first register. The method...
US20080082791 Providing temporary storage for contents of configuration registers  
In one embodiment, the present invention includes a method for assigning a first identifier to a first instruction that is to write control information into a configuration register, assigning the...
US20080016326 Latest producer tracking in an out-of-order processor, and applications thereof  
A processor and system for latest producer tracking. In one embodiment, the processor includes an operand renamer circuit that includes a register rename map, a producer tracking circuit that...
US20140281414 REORDER-BUFFER-BASED DYNAMIC CHECKPOINTING FOR RENAME TABLE REBUILDING  
Out-of-order CPUs, devices and methods diminish the time penalty from stalling the pipe to rebuild a rename table, such as due to a misprediction. A microprocessor can include a pipe that has a...
US20140013085 LOW POWER AND HIGH PERFORMANCE PHYSICAL REGISTER FREE LIST IMPLEMENTATION FOR MICROPROCESSORS  
A system and method for reducing latency and power of register renaming. A free list in processor includes multiple banks for indicating availability of register identifiers used for register...
US20140325188 SIMULTANEOUS FINISH OF STORES AND DEPENDENT LOADS  
A method for reducing a pipeline stall in a multi-pipelined processor includes finding a store instruction having a same target address as a load instruction and having a store value of the store...
US20140258687 MICRO-OPS INCLUDING PACKED SOURCE AND DESTINATION FIELDS  
A method and apparatus for register packing prior to register renaming in a microprocessor are provided. The method includes: receiving a plurality of micro operations (micro-ops) decoded from one...
US20140281393 REORDER-BUFFER-BASED STATIC CHECKPOINTING FOR RENAME TABLE REBUILDING  
Out-of-order CPUs, devices and methods diminish the time penalty from stalling the pipe to rebuild a rename table, such as due to a misprediction. A microprocessor can include a pipe that has a...
US20090037698 ADAPTIVE ALLOCATION OF RESERVATION STATION ENTRIES TO AN INSTRUCTION SET WITH VARIABLE OPERANDS IN A MICROPROCESSOR  
A method and device for adaptively allocating reservation station entries to an instruction set with variable operands in a microprocessor. The device includes logic for determining free...
US20060174093 System and method for event based interportlet communications  
In accordance with embodiments, there are provided mechanisms and methods for configuring and executing portlet responses to events within a web portal framework. These mechanisms and methods can...
US20070136562 Decoupling register bypassing from pipeline depth  
One embodiment of the present invention provides a system which decouples register bypassing from pipeline depth. The system starts by storing an intermediate result generated by an originating...
US20140380024 DEPENDENT INSTRUCTION SUPPRESSION  
A method includes suppressing execution of at least one dependent instruction of a load instruction by a processor using stored dependency information responsive to an invalid status of the load...
US20060095733 Hardware device for executing conditional instruction out-of-order fetch and execution method thereof  
A hardware device for executing conditional instructions out-of-order and the execution method. An architecture is provided, enabling the hardware device such as a processor supporting the...
US20140047219 Managing A Register Cache Based on an Architected Computer Instruction Set having Operand Last-User Information  
A multi-level register hierarchy is disclosed comprising a first level pool of registers for caching registers of a second level pool of registers in a system wherein programs can dynamically...
US20060095732 Processes, circuits, devices, and systems for scoreboard and other processor improvements  
A method of instruction issue (3200) in a microprocessor (1100, 1400, or 1500) with execution pipestages (E1, E2, etc.) and that executes a producer instruction Ip and issues a candidate...
US20050228971 Buffer virtualization  
A buffer virtualization mechanism to allow for a large number of allocate-able buffering resources. In particular, embodiments of the invention involve a tracking technique for implementing the...
US20050149698 Scoreboarding mechanism in a pipeline that includes replays and redirects  
An apparatus for a processor includes a first scoreboard, a second scoreboard, and a control circuit coupled to the first scoreboard and the second scoreboard. The control circuit is configured to...
US20100312993 REGISTER RENAMING TABLE RECOVERY METHOD AND SYSTEM  
A register renaming table recovery method for use in a processor includes the following steps. Firstly, a flushing operation is performed on a renaming-history table according to a flushed ID....
US20100205409 NOVEL REGISTER RENAMING SYSTEM USING MULTI-BANK PHYSICAL REGISTER MAPPING TABLE AND METHOD THEREOF  
Embodiments of a processor architecture utilizing multi-bank implementation of physical register mapping table are provided. A register renaming system to correlate architectural registers to...
US20100058035 System and Method for Double-Issue Instructions Using a Dependency Matrix  
A method for double-issue complex instructions receives a complex instruction comprising a first portion and a second portion. The method sets a single issue queue slot and allocates an execution...
US20080016325 Using windowed register file to checkpoint register state  
In one embodiment, a processor comprises a core configured to execute instructions; a register file comprising a plurality of storage locations; and a window management unit. The window management...
US20150127926 INSTRUCTION SCHEDULING APPROACH TO IMPROVE PROCESSOR PERFORMANCE  
A processor instruction scheduler comprising an optimization engine which uses an optimization model for a processor architecture with: means to generate an optimization model for the optimization...
US20120260072 REGISTER ALLOCATION IN ROTATION BASED ALIAS PROTECTION REGISTER  
A system may comprises an optimizer/scheduler to schedule on a set of instructions, compute a data dependence, a checking constraint and/or an anti-checking constraint for the set of scheduled...
US20140289501 TECHNIQUE FOR FREEING RENAMED REGISTERS  
Register renaming circuitry for a processing apparatus configured to process a stream of instructions from an instruction set specifying registers from an architectural set of registers. The...
US20090150653 Mechanism for soft error detection and recovery in issue queues  
In one embodiment, the present invention includes logic to detect a soft error occurring in certain stages of a core and recover from such error if detected. One embodiment may include logic to...
US20080301412 High speed multiplexer  
According to one embodiment, a high speed multiplexer includes a number of data inputs, a number of hot code select inputs, and a final data output. In one embodiment, the high speed multiplexer...
US20080040589 PROCESSOR DEVICE  
A processor device having a reservation station (RS) is concerned. In case the processor device has plural RS, the RS is associated with an arithmetic pipeline, and two RS make a pair. When one RS...
US20080256340 Distributed File Fuzzing  
Embodiments provide a distributed file fuzzing environment. In an embodiment, a number of computing devices can be used as part of a distributing fuzzing system. Fuzzing operations can be...
US20050120191 Checkpoint-based register reclamation  
A processor enabled with checkpoints may be used to recover registers using counter entry and release.
US20130145131 Flexible Microprocessor Register File  
Architectures and methods for viewing data in multiple formats within a register file. Various disclosed embodiments allow a plurality of consecutive registers within one register file to appear...
US20090327662 Managing active thread dependencies in graphics processing  
A scoreboard for a video processor may keep track of only dispatched threads which have not yet completed execution. A first thread may itself snoop for execution of a second thread that must be...
US20060149929 Processor with automatic scheduling of operations  
A high speed processor. The processor includes terminals that each execute a subset of the instruction set. In at least one of the terminals, the instructions are executed in an order determined...
US20080313435 Data processing apparatus and method for executing complex instructions  
A data processing apparatus and method are provided for executing complex instructions. The data processing apparatus executes instructions defining operations to be performed by the data...
US20070260856 Methods and apparatus to detect data dependencies in an instruction pipeline  
Example methods and apparatus to detect data dependencies in an instruction pipeline are disclosed. A disclosed example method uses an address pointer associated with a first instruction and...
US20080177983 Selective suppression of register renaming  
A register renaming unit 8 has mapping control circuitry 24 which serves to suppress unnecessary mapping operations in dependence upon a detected current state of the data processing system 2. One...
US20050076189 Method and apparatus for pipeline processing a chain of processing instructions  
Processor instruction pipelines, which split the processing of individual instructions into several sub-stages and thus reduce the complexity of each stage while simultaneously increasing the...
US20150234657 LATEST PRODUCER TRACKING IN AN OUT-OF-ORDER PROCESSOR, AND APPLICATIONS THEREOF  
A processor and system for latest producer tracking In one embodiment, the processor includes an operand renamer circuit that includes a register rename map, a producer tracking circuit that...
US20090327661 MECHANISMS TO HANDLE FREE PHYSICAL REGISTER IDENTIFIERS FOR SMT OUT-OF-ORDER PROCESSORS  
Methods and apparatus relating to mechanisms to handle free physical register identifiers for SMT (Simultaneous Multi-Threading) out-of-order processors are described. In some embodiments, a...
US20130339671 ZERO CYCLE LOAD  
A system and method for reducing the latency of load operations. A register rename unit within a processor determines whether a decoded load instruction is eligible for conversion to a zero-cycle...
US20060288193 Register-collecting mechanism for multi-threaded processors and method using the same  
A register-collecting mechanism and method using the same for multi-threaded processors are described. The register-collecting mechanism includes an instruction scanner, a register mapping table,...
US20150220341 SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING SOFTWARE-BASED SCOREBOARDING  
A system, method, and computer program product are provided for implementing a software-based scoreboarding mechanism. The method includes the steps of receiving a dependency barrier instruction...
US20080077777 Register renaming for instructions having unresolved condition codes  
Register renaming logic is disclosed that is operable to map registers from an architectural set of registers to registers within a physical set of registers, said architectural set of registers...

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