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US20140082330 ENHANCED INSTRUCTION SCHEDULING DURING COMPILATION OF HIGH LEVEL SOURCE CODE FOR IMPROVED EXECUTABLE CODE  
Systems and methods for static code scheduling are disclosed. A method can include receiving an intermediate representation of source code, building a directed acyclic graph (DAG) for the...
US20100299504 MICROPROCESSOR WITH MICROINSTRUCTION-SPECIFIABLE NON-ARCHITECTURAL CONDITION CODE FLAG REGISTER  
A microprocessor includes an architectural register and a non-architectural register, each having a plurality of condition code flags. A first instruction of the microarchitectural instruction set...
US20140201501 DYNAMIC ACCESSING OF EXECUTION ELEMENTS THROUGH MODIFICATION OF ISSUE RULES  
Embodiments of the invention relate to dynamically routing instructions to execution units based on detected errors in the execution units. An aspect of the invention includes a computer system...
US20110320771 INSTRUCTION UNIT WITH INSTRUCTION BUFFER PIPELINE BYPASS  
A circuit arrangement and method selectively bypass an instruction buffer for selected instructions so that bypassed instructions can be dispatched without having to first pass through the...
US20150089198 TECHNIQUE FOR REDUCING VOLTAGE DROOP BY THROTTLING INSTRUCTION ISSUE RATE  
An issue control unit is configured to control the rate at which an instruction issue unit issues instructions to an execution pipeline in order to avoid spikes in power drawn by that execution...
US20100306504 Controlling issue and execution of instructions having multiple outcomes  
At least one instruction of a sequence of program instructions has a plurality of alternative outcomes including at least a first outcome that is independent of at least one operand and a second...
US20130283013 METHOD AND APPARATUS FOR AGENT INTERFACING WITH PIPELINE BACKBONE TO LOCALLY HANDLE TRANSACTIONS WHILE OBEYING ORDERING RULE  
In accordance with embodiments disclosed herein, there are provided methods, systems, and apparatuses for enabling an agent interfacing with a pipelined backbone to locally handle transactions...
US20060036834 Trace reuse  
A trace management architecture to enable the reuse of uops within one or more repeated traces. More particularly, embodiments of the invention relate to a technique to prevent multiple accesses...
US20140068228 INSTRUCTION FORWARDING BASED ON PREDICATION CRITERIA  
Embodiments herein relate to forwarding an instruction based on predication criteria. A predicate state associated with a packet of data is to be compared to an instruction associated with the...
US20150026436 HYBRID TAG SCHEDULER  
The present invention provides a method and apparatus for scheduling based on tags of different types. Some embodiments of the method include broadcasting a first tag to entries in a queue of a...
US20050149709 Prediction based indexed trace cache  
A system and method for compensating for branching instructions in trace caches is disclosed. A branch predictor uses the branching behavior of previous branching instructions to select between...
US20140052965 DYNAMIC CPU GPU LOAD BALANCING USING POWER  
Dynamic CPU GPU load balancing is described based on power. In one example, an instruction is received and power values are received for a central processing core (CPU) and a graphics processing...
US20140189313 QUEUED INSTRUCTION RE-DISPATCH AFTER RUNAHEAD  
Various embodiments of microprocessors and methods of operating a microprocessor during runahead operation are disclosed herein. One example method of operating a microprocessor includes...
US20100250901 Selecting Fixed-Point Instructions to Issue on Load-Store Unit  
Issue logic identifies a simple fixed point instruction, included in a unified payload, which is ready to issue. The simple fixed point instruction is a type of instruction that is executable by...
US20070204137 Multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture  
A multi-threaded microprocessor (1105) for processing instructions in threads. The microprocessor (1105) includes first and second decode pipelines (1730.0, 1730.1), first and second execute...
US20130339669 NONTRANSACTIONAL STORE INSTRUCTION  
A NONTRANSACTIONAL STORE instruction, executed in transactional execution mode, performs stores that are retained, even if a transaction associated with the instruction aborts. The stores include...
US20130185542 EXTERNAL AUXILIARY EXECUTION UNIT INTERFACE TO OFF-CHIP AUXILIARY EXECUTION UNIT  
An external Auxiliary Execution Unit (AXU) interface is provided between a processing core disposed in a first programmable chip and an off-chip AXU disposed in a second programmable chip to...
US20150262074 SOLVING DIGITAL LOGIC CONSTRAINT PROBLEMS VIA ADIABATIC QUANTUM COMPUTATION  
A constraint problem may be represented as a digital circuit comprising at least one gate and at least one constrained input or at least one constrained output, or a combination of at least one...
US20050125632 Transitioning from instruction cache to trace cache on label boundaries  
Various embodiments of methods and systems for implementing a microprocessor that includes a trace cache and attempts to transition fetching from instruction cache to trace cache only on label...
US20150113251 Systems and Methods for Register Allocation  
System and methods are provided for register allocation. An original code block and a target code block associated with a branch of an execution loop are determined. An original allocation of a...
US20100325394 System and Method for Balancing Instruction Loads Between Multiple Execution Units Using Assignment History  
A system and method for balancing instruction loads between multiple execution units are disclosed. One or more execution units may be represented by a slot configured to accept instructions on...
US20140325187 SINGLE-CYCLE INSTRUCTION PIPELINE SCHEDULING  
A method includes allocating a first single-cycle instruction to a first pipeline that picks single-cycle instructions for execution in program order. The method further includes marking at least...
US20090217006 Heuristic backtracer  
A heuristic backtracer is described. In one embodiment, a scanner scans a stack of an application for a pointer to a word of a machine code of the application. A preceding byte locator identifies...
US20110072243 Unified Collector Structure for Multi-Bank Register File  
One embodiment of the present invention sets forth a technique for collecting operands specified by an instruction. As a sequence of instructions is received the operands specified by the...
US20090254784 SEMICONDUCTOR MEMORY DEVICE AND SYSTEM USING SEMICONDUCTOR MEMORY DEVICE  
A semiconductor memory device comprises a RAM (Random Access Memory), an ODT (On-Die Termination) circuits and a JTAG (Joint Test Action Group) circuit. The RAM is connected to a data input-output...
US20140129805 EXECUTION PIPELINE POWER REDUCTION  
Systems and methods for reducing power consumption by an execution pipeline are provided. In one example, a method includes stalling an operation from being executed in the execution pipeline...
US20140310506 ALLOCATING STORE QUEUE ENTRIES TO STORE INSTRUCTIONS FOR EARLY STORE-TO-LOAD FORWARDING  
The present invention provides a method and apparatus for allocating store queue entries to store instructions for early store-to-load forwarding. Some embodiments of the method include allocating...
US20070043932 Wakeup mechanisms for schedulers  
Methods and apparatus to provide wakeup mechanisms for schedulers are described. In one embodiment, a scheduler broadcasts a uop scheduler identifier of a scheduled uop (or micro-operation) to one...
US20060179279 Bifurcated thread scheduler in a multithreading microprocessor  
A bifurcated instruction scheduler for dispatching instructions of multiple threads concurrently executing in a multithreading processor is provided. The scheduler includes a first portion within...
US20100100712 Multi-Execution Unit Processing Unit with Instruction Blocking Sequencer Logic  
A processing unit includes multiple execution units and sequencer logic that is disposed downstream of instruction buffer logic, and that is responsive to a sequencer instruction present in an...
US20090182986 Processing Unit Incorporating Issue Rate-Based Predictive Thermal Management  
A circuit arrangement and method utilize an issue rate-based predictive thermal management technique in a microprocessor or other integrated circuit that tracks the rate in which instructions are...
US20120204009 MULTI-LEVEL REGISTER FILE SUPPORTING MULTIPLE THREADS  
A processor includes an instruction fetch unit, an issue queue coupled to the instruction fetch unit, an execution unit coupled to the issue queue, and a multi-level register file including a...
US20120072700 MULTI-LEVEL REGISTER FILE SUPPORTING MULTIPLE THREADS  
A processor includes an instruction fetch unit, an issue queue coupled to the instruction fetch unit, an execution unit coupled to the issue queue, and a multi-level register file including a...
US20130346729 PIPELINING OUT-OF-ORDER INSTRUCTIONS  
Systems, methods and computer program product provide for pipelining out-of-order instructions. Embodiments comprise an instruction reservation station for short instructions of a short latency...
US20110252220 INSTRUCTION CRACKING AND ISSUE SHORTENING BASED ON INSTRUCTION BASE FIELDS, INDEX FIELDS, OPERAND FIELDS, AND VARIOUS OTHER INSTRUCTION TEXT BITS  
A method, information processing system, and computer program product crack and/or shorten computer executable instructions. At least one instruction is received. The at least on instruction is...
US20080133889 HIERARCHICAL INSTRUCTION SCHEDULER  
A hierarchical instruction scheduler included in a hierarchical microprocessor comprising a plurality of execution clusters. In one embodiment, a hierarchical instruction scheduler comprises a...
US20130305022 Speeding Up Younger Store Instruction Execution after a Sync Instruction  
Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of...
US20070186081 Supporting out-of-order issue in an execute-ahead processor  
One embodiment of the present invention provides a system which supports out-of-order issue in a processor that normally executes instructions in-order. The system starts by issuing instructions...
US20080222394 Systems and Methods for TDM Multithreading  
Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for...
US20140281402 PROCESSOR WITH HYBRID PIPELINE CAPABLE OF OPERATING IN OUT-OF-ORDER AND IN-ORDER MODES  
A method and circuit arrangement provide support for a hybrid pipeline that dynamically switches between out-of-order and in-order modes. The hybrid pipeline may selectively execute instructions...
US20110072244 Credit-Based Streaming Multiprocessor Warp Scheduling  
One embodiment of the present invention sets forth a technique for ensuring cache access instructions are scheduled for execution in a multi-threaded system to improve cache locality and system...
US20140351562 TECHNIQUES FOR SCHEDULING OPERATIONS AT AN INSTRUCTION PIPELINE  
A dispatch stage of a processor core dispatches designated operations (e.g. load/store operations) to a temporary queue when the resources to execute the designated operations are not available....
US20090070558 MULTIPLEXING PER-PROBEPOINT INSTRUCTION SLOTS FOR OUT-OF-LINE EXECUTION  
The present invention provides a probe system and method for multithreaded user-space programs. The system includes an instrumentation module that enables single stepping out of line processing...
US20080148021 High Frequency Stall Design  
An issue unit includes a first instruction stage, a second instruction stage, and issue control logic. During a first instruction cycle, the issue unit performs two tasks, which are 1) the...
US20080320282 Method And Systems For Providing Transaction Support For Executable Program Components  
Methods and systems are described for providing transaction support for executable program components. In one embodiment, transaction information is associated with an instruction included in an...
US20090282221 Preferential Dispatching Of Computer Program Instructions  
A computer processor that includes a plurality of execution pipelines, each execution pipeline including a configuration of one or more execution units of the processor, each execution pipeline...
US20080301694 COMMUNICATION SCHEDULING WITHIN A PARALLEL PROCESSING SYSTEM  
Within a data processing system, one or more register files are assigned to respective states of a graph for each of a plurality of clock cycles. A plurality of edges are inserted to form...
US20140281403 CHAINING BETWEEN EXPOSED VECTOR PIPELINES  
Embodiments include a method for chaining data in an exposed-pipeline processing element. The method includes separating a multiple instruction word into a first sub-instruction and a second...
US20090271592 Apparatus For Storing Instructions In A Multithreading Microprocessor  
A circuit for selecting one of N requesters in a round-robin fashion is disclosed. The circuit 1-bit left rotatively increments a first addend by a second addend to generate a sum that is ANDed...
US20140189312 PROGRAMMABLE HARDWARE ACCELERATORS IN CPU  
Embodiments of the present invention may include a data processing system comprising a processing execution block to execute instructions stored in an instruction queue, a programmable hardware...

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