Matches 201 - 233 out of 233 < 1 2 3 4 5


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US20160283248 SCHEDULERS WITH LOAD-STORE QUEUE AWARENESS  
In one embodiment, a computer-implemented method includes tracking a size of a load-store queue (LSQ) during compile time of a program. The size of the LSQ is time-varying and indicates how many...
US20160253179 CONCURRENT EXECUTION OF HETEROGENEOUS VECTOR INSTRUCTIONS  
A processor may include a vector functional unit that supports concurrent operations on multiple data elements of a maximum element size. The functional unit may also support concurrent execution...
US20160239308 LOAD QUEUE ENTRY REUSE FOR OPERAND STORE COMPARE HISTORY TABLE UPDATE  
Embodiments relate to load queue entry reuse for operand store compare (OSC) history table update. An aspect includes allocating a load queue entry in a load queue to a load instruction that is...
US20160239307 LOAD QUEUE ENTRY REUSE FOR OPERAND STORE COMPARE HISTORY TABLE UPDATE  
Embodiments relate to load queue entry reuse for operand store compare (OSC) history table update. An aspect includes allocating a load queue entry in a load queue to a load instruction that is...
US20160239306 DYNAMIC RESOURCE ALLOCATION ACROSS DISPATCH PIPES  
Dynamic resource allocation is provided in which additional resources, such as additional architected registers, are provided to an instruction, if it is determined that resources in addition to...
US20160202988 PARALLEL SLICE PROCESSING METHOD USING A RECIRCULATING LOAD-STORE QUEUE FOR FAST DEALLOCATION OF ISSUE QUEUE ENTRIES  
A method of operation of a processor core execution unit circuit provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The...
US20160170766 PROGRAMMABLE LOAD REPLAY PRECLUDING MECHANISM  
An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a...
US20160154653 MEMORY FRAGMENTS FOR SUPPORTING CODE BLOCK EXECUTION BY USING VIRTUAL CORES INSTANTIATED BY PARTITIONABLE ENGINES  
A system for executing instructions using a plurality of memory fragments for a processor. The system includes a global front end scheduler for receiving an incoming instruction sequence, wherein...
US20160092231 INDEPENDENT MAPPING OF THREADS  
Embodiments of the present invention provide systems and methods for mapping the architected state of one or more threads to a set of distributed physical register files to enable independent...
US20160070576 SPECULATIVE REGISTER FILE READ SUPPRESSION  
A single threaded out-of-order processor 2 includes an architected register file 22 and a speculative register file 20. Speculative register allocation circuitry 24 serves to allocate speculative...
US20160070574 REGISTER FILES FOR STORING DATA OPERATED ON BY INSTRUCTIONS OF MULTIPLE WIDTHS  
A processor core includes even and odd execution slices each having a register file. The slices are each configured to perform operations specified in a first set of instructions on data from its...
US20160041828 METHOD AND SYSTEM FOR GENERATING OBJECT CODE TO FACILITATE PREDICTIVE MEMORY RETRIEVAL  
A method and system are described for generating reference tables in object code which specify the addresses of branches, routines called, and data references used by routines in the code. In a...
US20150370572 Multi-User Processor System for Processing Information  
This multi-user processor system for processing information, of the type including a data exchange engine (3) associated with multiple users (1) of shared resources (2), is characterized in that...
US20150370569 INSTRUCTION PROCESSING SYSTEM AND METHOD  
An instruction processing system is provided. The system includes a central processing unit (CPU), an m number of memory devices and an instruction control unit. The CPU is capable of being...
US20150363206 IMPLEMENTING OUT OF ORDER PROCESSOR INSTRUCTION ISSUE QUEUE  
A method and apparatus are provided for implementing an enhanced out of order processor instruction issue queue in a computer system. Instructions are selectively accepted into an instruction...
US20150363205 IMPLEMENTING OUT OF ORDER PROCESSOR INSTRUCTION ISSUE QUEUE  
A method and apparatus are provided for implementing an enhanced out of order processor instruction issue queue in a computer system. Instructions are selectively accepted into an instruction...
US20150301831 SELECT LOGIC FOR THE INSTRUCTION SCHEDULER OF A MULTI STRAND OUT-OF-ORDER PROCESSOR BASED ON DELAYED RECONSTRUCTED PROGRAM ORDER  
A processing device comprises select logic to schedule a plurality of instructions for execution. The select logic calculates a reconstructed program order (RPO) value for each of a plurality of...
US20150286484 PROCESSOR SUBROUTINE CACHE  
A processor includes an execution unit and a subroutine cache. The execution unit is configured to execute instructions. The subroutine cache us configured to provide instructions of a subroutine...
US20150220345 VECTOR MASK DRIVEN CLOCK GATING FOR POWER EFFICIENCY OF A PROCESSOR  
A processor includes an instruction schedule and dispatch (schedule/dispatch) unit to receive a single instruction multiple data (SIMD) instruction to perform an operation on multiple data...
US20150178088 HONORING HARDWARE ENTITLEMENT OF A HARDWARE THREAD  
A method for scheduling the execution of a computer instruction, receive an entitlement processor resource percentage for a logical partition on a computer system. The logical partition is...
US20150074379 System and Method for an Asynchronous Processor with Token-Based Very Long Instruction Word Architecture  
Embodiments are provided for an asynchronous processor with token-based very long instruction word architecture. The asynchronous processor comprises a memory configured to cache a plurality of...
US20140289500 METHOD AND APPARATUS FOR PROVIDING AN INTERFACE BETWEEN A UICC AND A PROCESSOR IN AN ACCESS TERMINAL THAT SUPPORTS ASYNCHRONOUS COMMAND PROCESSING BY THE UICC  
Techniques for providing an interface between a UICC and a processor, included in an access terminal, that supports asynchronous command processing by the UICC, are described. A first complex...
US20120303937 COMPUTER SYSTEM AND CONTROL METHOD THEREOF  
A computer system used to execute an application includes a motion sensing unit, a processor and an instruction transfer unit. The motion sensing unit senses a gesture of a human body and...
US20120272045 CONTROL METHOD AND SYSTEM OF MULTIPROCESSOR  
A control method and a system for dispatching the execution sequence of the processes in a multiprocessors system so as to dispatch an operation sequence for executing different operation programs...
US20120246448 MEMORY FRAGMENTS FOR SUPPORTING CODE BLOCK EXECUTION BY USING VIRTUAL CORES INSTANTIATED BY PARTITIONABLE ENGINES  
A system for executing instructions using a plurality of memory fragments for a processor. The system includes a global front end scheduler for receiving an incoming instruction sequence, wherein...
US20120096243 MULTITHREADED PROCESSOR WITH MULTIPLE CONCURRENT PIPELINES PER THREAD  
A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of...
US20120066472 MACROSCALAR PROCESSOR ARCHITECTURE  
A macroscalar processor architecture is described herein. In one embodiment, a processor receives instructions of a program loop having a vector block and a sequence block intended to be executed...
US20110246995 CACHE-AWARE THREAD SCHEDULING IN MULTI-THREADED SYSTEMS  
The disclosed embodiments provide a system that facilitates scheduling threads in a multi-threaded processor with multiple processor cores. During operation, the system executes a first thread in...
US20110225398 ADVANCED PROCESSOR SCHEDULING IN A MULTITHREADED SYSTEM  
An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores...
US20110099354 Information processing apparatus and instruction decoder for the information processing apparatus  
An information processing apparatus includes an instruction supplying section that supplies a plurality of instructions as a single instruction group, an executing section that repetitively...
US20110078416 APPARATUS AND METHOD FOR CONTROL PROCESSING IN DUAL PATH PROCESSOR  
A computer processor comprises a decode unit and a processing channel. The decode unit decodes a stream of instruction packets from a memory, each instruction packet comprising a plurality of...
US20110078414 MULTIPORTED REGISTER FILE FOR MULTITHREADED PROCESSORS AND PROCESSORS EMPLOYING REGISTER WINDOWS  
A processor includes an instruction fetch unit configured to issue instructions for execution, where the instructions are selected from a number of threads, where each given instruction has a...
US20100318769 USING VECTOR ATOMIC MEMORY OPERATION TO HANDLE DATA OF DIFFERENT LENGTHS  
A system and method of compiling program code, wherein the program code includes an operation on an array of data elements stored in memory of a computer system. The program code is scanned for an...

Matches 201 - 233 out of 233 < 1 2 3 4 5