Matches 101 - 150 out of 233 < 1 2 3 4 5 >


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US20080162887 SYSTEM FOR GENERATING EFFECTIVE ADDRESS  
Method, system and computer program product for generating effective addresses in a data processing system. A method, in a data processing system, for generating an effective address includes...
US20120023314 PAIRED EXECUTION SCHEDULING OF DEPENDENT MICRO-OPERATIONS  
A method and mechanism for reducing latency of a multi-cycle scheduler within a processor. A processor comprises a front end pipeline that determines data dependencies between instructions prior...
US20130138925 PROCESSING CORE WITH SPECULATIVE REGISTER PREPROCESSING  
A method and circuit arrangement speculatively preprocess data stored in a register file during otherwise unused cycles in an execution unit, e.g., to prenormalize denormal floating point values...
US20080162886 Handling precompiled binaries in a hardware accelerated software transactional memory system  
A method and apparatus for enabling a Software Transactional Memory (STM) with precompiled binaries is herein described. Upon encountering an access operation in a transaction, an annotation field...
US20070266224 Method and Computer Program Product for Executing a Program on a Processor Having a Multithreading Architecture  
The method for executing a program on a processor having a multithreading architecture includes identifying at least two processes of the program, the processes being executable independently of...
US20060206740 Systems and methods for controlling instruction throughput  
Systems and methods for controlling instruction throughput are disclosed. One embodiment of a system may comprise a comparator that determines a difference value in an actual instructions per...
US20090113179 OPERATIONAL PROCESSING APPARATUS, PROCESSOR, PROGRAM CONVERTING APPARATUS AND PROGRAM  
The present invention provides an operational processing apparatus which can guarantee a period for executing instructions in the shortest cycle when the operational processing apparatus...
US20110153991 DUAL ISSUING OF COMPLEX INSTRUCTION SET INSTRUCTIONS  
A system and method for issuing a processor instruction to multiple processing sections arranged in an out-of-order processing pipeline architecture. The multiple processing sections include a...
US20100262808 MANAGING INSTRUCTIONS FOR MORE EFFICIENT LOAD/STORE UNIT USAGE  
The illustrative embodiments described herein provide a computer-implemented method, apparatus, and a system for managing instructions. A load/store unit receives a first instruction at a port....
US20100228955 METHOD AND APPARATUS FOR IMPROVED POWER MANAGEMENT OF MICROPROCESSORS BY INSTRUCTION GROUPING  
A method of power gating a microprocessor having an instruction scheduling unit for receiving issued instructions from an instruction decode unit; an execution unit coupled to receive and send...
US20100332804 UNIFIED HIGH-FREQUENCY OUT-OF-ORDER PICK QUEUE WITH SUPPORT FOR SPECULATIVE INSTRUCTIONS  
Systems and methods for efficient picking of instructions for out-of-order issue and execution in a processor. In one embodiment, a processor comprises a unified pick queue that is dynamically...
US20070083735 Hierarchical processor  
Various embodiments are described relating to hierarchical processors.
US20130326197 ISSUING INSTRUCTIONS TO EXECUTION PIPELINES BASED ON REGISTER-ASSOCIATED PREFERENCES, AND RELATED INSTRUCTION PROCESSING CIRCUITS, PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA  
Issuing instructions to execution pipelines based on register-associated preferences and related instruction processing circuits, systems, methods, and computer-readable media are disclosed. In...
US20110296143 PIPELINE PROCESSOR AND AN EQUAL MODEL CONSERVATION METHOD  
A pipeline processor which meets a latency restriction on an equal model is provided. The pipeline processor includes a pipeline processing unit to process an instruction at a plurality of stages...
US20100312992 MULTITHREAD EXECUTION DEVICE AND METHOD FOR EXECUTING MULTIPLE THREADS  
A multithread execution device includes: a program memory in which a plurality of programs are stored; an instruction issue unit that issues an instruction retrieved from the program memory; an...
US20090300329 VOLTAGE DROOP MITIGATION THROUGH INSTRUCTION ISSUE THROTTLING  
A system and method for providing a digital real-time voltage droop detection and subsequent voltage droop reduction. A scheduler within a reservation station may store a weight value for each...
US20130145127 ZERO VALUE PREFIXES FOR OPERANDS OF DIFFERING BIT-WIDTHS  
A data processing system is provided in which destination operands to be stored within architectural registers are constrained to have zero values added as prefixes in order that the architectural...
US20140089589 BARRIER COLORS  
Methods and processors for enforcing an order of memory access requests in the presence of barriers in an out-of-order processor pipeline. A speculative color is assigned to instruction operations...
US20070022272 Microprocessor  
The present invention includes a pipeline having a plurality of stages, and a resource management unit configured to be connected to the pipeline and manage circuit resources for processing...
US20120191951 MFENCE and LFENCE Micro-Architectural Implementation Method and System  
A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions...
US20080209176 Time stamping transactions to validate atomic operations in multiprocessor systems  
A multi-core microprocessor has a plurality of processor cores which are coupled to a bridge element. The bridge element sends transactions to and/or receives transactions from the processor...
US20090177867 Processor architectures for enhanced computational capability  
A digital signal processor includes a control block configured to issue instructions based on a stored program, and a compute array including two or more compute engines configured such that each...
US20090240919 PROCESSOR AND METHOD FOR SYNCHRONOUS LOAD MULTIPLE FETCHING SEQUENCE AND PIPELINE STAGE RESULT TRACKING TO FACILITATE EARLY ADDRESS GENERATION INTERLOCK BYPASS  
A pipelined processor including an architecture for address generation interlocking, the processor including: an instruction grouping unit to detect a read-after-write dependency and to resolve...
US20070043930 Performance of a data processing apparatus  
Techniques for improving the performance of a data processing apparatus are disclosed. A data processing apparatus operable to process instructions and operable to determine, prior to each...
US20120191950 PREDICTING A RESULT FOR A PREDICATE-GENERATING INSTRUCTION WHEN PROCESSING VECTOR INSTRUCTIONS  
The described embodiments provide a processor that executes vector instructions. In the described embodiments, while dispatching instructions at runtime, the processor encounters a...
US20090055626 METHOD OF SHARING COARSE GRAINED ARRAY AND PROCESSOR USING THE METHOD  
A method of sharing a coarse grained array and a processor using the method is provided. A processor includes a first processor core including a plurality of first functional units which execute a...
US20080189520 USING PERFORMANCE DATA FOR INSTRUCTION THREAD DIRECTION  
A method for dispatching instructions in the data processing system, having in memory for storing instructions and a plurality of central processing units, where each central processing unit...
US20080046692 Method and Apparatus for Executing Processor Instructions Based on a Dynamically Alterable Delay  
Instruction execution delay is alterable after the system design has been finalized, thus enabling the system to dynamically account for various conditions that impact instruction execution. In...
US20100250966 PROCESSOR AND METHOD FOR IMPLEMENTING INSTRUCTION SUPPORT FOR HASH ALGORITHMS  
A processor including instruction support for implementing hash algorithms may issue, for execution, programmer-selectable hash instructions from a defined instruction set architecture (ISA). The...
US20100077181 System and Method for Issuing Load-Dependent Instructions in an Issue Queue in a Processing Unit of a Data Processing System  
A system and method for issuing load-dependent instructions in an issue queue in a processing unit. A load miss queue is provided. The load miss queue comprises a physical address field, an issue...
US20080046696 Non-Intrusive Method for Replaying Internal Events In An Application Process, And System Implementing This Method  
This invention relates to a method for replaying, from a log file, internal events within a process belonging to a software application in a network. This method comprising the following steps:...
US20100250900 DEPENDENCY TRACKING FOR ENABLING SUCCESSIVE PROCESSOR INSTRUCTIONS TO ISSUE  
An information handling system includes a processor with an issue unit (IU) that may perform instruction dependency tracking for successive instruction issue operations. The IU maintains...
US20100246815 APPARATUS AND METHOD FOR IMPLEMENTING INSTRUCTION SUPPORT FOR THE KASUMI CIPHER ALGORITHM  
A processor including instruction support for implementing the Kasumi block cipher algorithm may issue, for execution, programmer-selectable instructions from a defined instruction set...
US20140122844 INTELLIGENT CONTEXT MANAGEMENT  
Intelligent context management for thread switching is achieved by determining that a register bank has not been used by a thread for a predetermined number of dispatches, and responsively...
US20060200648 HIGH-LEVEL LANGUAGE PROCESSOR APPARATUS AND METHOD  
A digital computing component and method for computing configured to execute the constructs of a high-level software programming language via optimizing hardware targeted at the particular...
US20060195679 Processing apparatus  
A processing apparatus includes an execution stage which executes each of instruction streams, a first resource counter which counts the number of operating resources used when the execution stage...
US20100306505 Result path sharing between a plurality of execution units within a processor  
A processor 2 includes an execution cluster 10 having multiple execution units 14, 16, 18, 20. The execution units 14, 16, 18, 20 share result buses 22, 24. Issue circuitry 12 within the execution...
US20130262823 INSTRUCTION MERGING OPTIMIZATION  
A computer system for optimizing instructions includes a processor including an instruction execution unit configured to execute instructions and an instruction optimization unit configured to...
US20130191616 INSTRUCTION CONTROL CIRCUIT, PROCESSOR, AND INSTRUCTION CONTROL METHOD  
In a vector processing device, a data dependence detecting unit detects a data dependence relation between a preceding instruction and a succeeding instruction which are inputted from an...
US20120246447 Region-Weighted Accounting of Multi-Threaded Processor Core According to Dispatch State  
According to one embodiment of the present disclosure, an approach is provided in which a thread is selected from multiple active threads, along with a corresponding weighting value. Computational...
US20100257339 Dependency Matrix with Improved Performance  
A processor having a dependency matrix comprises a first array comprising a plurality of cells arranged in a plurality of columns and a plurality of rows. Each row represents an instruction in a...
US20130111191 PROCESSOR INSTRUCTION ISSUE THROTTLING  
A system and method for reducing power consumption through issue throttling of selected problematic instructions. A power throttle unit within a processor maintains instruction issue counts for...
US20080256337 Method of Decoding A Bit Sequence, Network Element Apparatus And PDU Specification Tool Kit  
In the field of data communications, it is desirable to track bits of a bit sequence remaining to be decoded by a decoder. A method of decoding the bit sequence that corresponds to a PDU comprises...
US20100250905 System and Method of Routing Instructions  
Disclosed are a method and system for reducing complexity of routing of instructions from an instruction issue queue to appropriate execution pipelines in a superscalar processor. In one or more...
US20110055523 EARLY BRANCH DETERMINATION  
A method and apparatus for branch determination. The method includes a first command issuing within a computer processor, wherein execution of the first command by the computer processor includes...
US20110296142 PROCESSOR AND METHOD PROVIDING INSTRUCTION SUPPORT FOR INSTRUCTIONS THAT UTILIZE MULTIPLE REGISTER WINDOWS  
A processor including instruction support for large-operand instructions that use multiple register windows may issue, for execution, programmer-selectable instructions from a defined instruction...
US20130046954 MULTI-THREADED DFA ARCHITECTURE  
Disclosed is an architecture, system and method for performing multi-thread DFA descents on a single input stream. An executer performs DFA transitions from a plurality of threads each starting at...
US20100205406 OUT-OF-ORDER EXECUTION MICROPROCESSOR THAT SPECULATIVELY EXECUTES DEPENDENT MEMORY ACCESS INSTRUCTIONS BY PREDICTING NO VALUE CHANGE BY OLDER INSTRUCTIONS THAT LOAD A SEGMENT REGISTER  
An out-of-order execution microprocessor executes an architectural segment register-loading instruction that instructs the microprocessor to load a new value into an architectural segment register...
US20110208950 PROCESSES, CIRCUITS, DEVICES, AND SYSTEMS FOR SCOREBOARD AND OTHER PROCESSOR IMPROVEMENTS  
A method of instruction issue (3200) in a microprocessor (1100, 1400, or 1500) with execution pipestages (E1, E2, etc.) and that executes a producer instruction Ip and issues a candidate...
US20100106945 Instruction processing apparatus  
The present invention includes a decode section for simultaneously holding a plurality of instructions in one thread at a time and for decoding the held instructions; an execution pipeline capable...

Matches 101 - 150 out of 233 < 1 2 3 4 5 >