Matches 51 - 100 out of 233 < 1 2 3 4 5 >


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US20130166885 METHOD AND APPARATUS FOR ON-CHIP TEMPERATURE  
When an instruction is executed on an integrated circuit (IC), an activity level and temperature are measured. A relationship between the activity level and temperature is determined, to estimate...
US20090037697 SYSTEM AND METHOD OF LOAD-STORE FORWARDING  
A system and method for data forwarding from a store instruction to a load instruction during out-of-order execution, when the load instruction address matches against multiple older uncommitted...
US20150095618 VIRTUAL LOAD STORE QUEUE HAVING A DYNAMIC DISPATCH WINDOW WITH A UNIFIED STRUCTURE  
An out of order processor. The processor includes a virtual load store queue for allocating a plurality of loads and a plurality of stores, wherein more loads and more stores can be accommodated...
US20110314260 HIGH-WORD FACILITY FOR EXTENDING THE NUMBER OF GENERAL PURPOSE REGISTERS AVAILABLE TO INSTRUCTIONS  
A computer employs a set of General Purpose Registers (GPRs). Each GPR comprises a plurality of portions. Programs such as an Operating System and Applications operating in a Large GPR mode,...
US20130117541 SPECULATIVE EXECUTION AND ROLLBACK  
One embodiment of the present invention sets forth a technique for speculatively issuing instructions to allow a processing pipeline to continue to process some instructions during rollback of...
US20080046695 System controller, identical-address-request-queuing preventing method, and information processing apparatus having identical-address-request-queuing preventing function  
In a system controller including a CPU-issued request queue having a circuit that processes plural requests having identical addresses not to be inputted to the CPU-issued request queue, a latest...
US20100064287 Scheduling control within a data processing system  
A processor 2 is responsive to a stream of program instructions to issue program instructions under control of scheduling circuitry 6 to respective execution units 24 for execution. The execution...
US20120331273 Reduced Instruction Set  
A method of reducing a set of instructions for execution on a processor, the method comprising: extracting information from a first instruction of the set of instructions; identifying unencoded...
US20140372732 ACCELERATED REVERSAL OF SPECULATIVE STATE CHANGES AND RESOURCE RECOVERY  
A method includes undoing, in reverse program order, changes in a state of a processing device caused by speculative instructions previously dispatched for execution in the processing device and...
US20070101102 Selectively pausing a software thread  
A method, system and computer-usable medium are presented for pausing a software thread in a process. An instruction from a first software thread in the process is sent to an Instruction...
US20080162885 Mechanism for software transactional memory commit/abort in unmanaged runtime environment  
A method and apparatus for ensuring integrity of transaction exit functions is herein described. Dead local data in a transaction is prevented from overwriting local variables associated with a...
US20090327660 MEMORY THROUGHPUT INCREASE VIA FINE GRANULARITY OF PRECHARGE MANAGEMENT  
Methods and apparatus to improve throughput in memory devices are described. In one embodiment, memory throughput is increased via fine granularity of precharge management. In an embodiment, three...
US20080140999 PROGRAMMABLE VIDEO SIGNAL PROCESSOR FOR VIDEO COMPRESSION AND DECOMPRESSION  
A data processing method with multiple issue multiple datapath architecture in a video signal processor (VSP) is provided. In the method, commands are received from the external signal processor....
US20110138152 INSTRUCTION CONTROL DEVICE  
A processor which executes threads having different characteristics is provided with an instruction control device. In the instruction control device, a first instruction control unit issues an...
US20100251016 Issuing Instructions In-Order in an Out-of-Order Processor Using False Dependencies  
A mechanism is provided for issuing instructions. An instruction dispatch unit receives an instruction for dispatch to one of a plurality of execution units. The instruction dispatch unit analyzes...
US20120204008 Processor with a Hybrid Instruction Queue with Instruction Elaboration Between Sections  
Methods and apparatus for processing instructions by elaboration of instructions prior to issuing the instructions for execution are described. An instruction is received at a hybrid instruction...
US20050071603 Apparatus and method for power optimized replay  
A method and apparatus for power optimized replay. In one embodiment, the method includes the issuance of an instruction selected from a queue. Once issued, the instruction may be enqueued within...
US20090249034 PROCESSOR AND SIGNATURE GENERATION METHOD, AND MULTIPLE SYSTEM AND MULTIPLE EXECUTION VERIFICATION METHOD  
A processor performs instruction execution regardless of a program order. An execution unit executes an instruction, and transmits end information of the instruction whose execution has ended. A...
US20080072017 Processing System having a Plurality of Processing Units with Program Counters and Related Method for Processing Instructions in the Processing System  
A method for processing predetermined instructions in a processing system having a plurality of processing units includes providing a global program counter and setting a counter value of the...
US20100250902 Tracking Deallocated Load Instructions Using a Dependence Matrix  
A mechanism is provided for tracking deallocated load instructions. A processor detects whether a load instruction in a set of instructions in an issue queue has missed. Responsive to a miss of...
US20090119490 PROCESSOR AND INSTRUCTION SCHEDULING METHOD  
An instruction scheduling method and a processor using an instruction scheduling method are provided. The instruction scheduling method includes selecting a first instruction that has a highest...
US20090249026 Vector instructions to enable efficient synchronization and parallel reduction operations  
In one embodiment, a processor may include a vector unit to perform operations on multiple data elements responsive to a single instruction, and a control unit coupled to the vector unit to...
US20070245128 Cache metadata for accelerating software transactional memory  
Various technologies and techniques are disclosed for providing a hardware accelerated software transactional memory application. The software transactional memory application has access to...
US20110004743 Pipe scheduling for pipelines based on destination register number  
A data processing apparatus 1 has a plurality of registers 10 of the same type of register and a plurality of processing pipelines 40, 50, each processing pipeline 40, 50 being arranged to process...
US20070204135 Distributive scoreboard scheduling in an out-of order processor  
A processor core and a method for distributive scoreboard scheduling in an out-of-order processor pipeline. In an embodiment, control logic appends operand availability bits to each instruction....
US20100082947 VERY-LONG INSTRUCTION WORD ARCHITECTURE WITH MULTIPLE PROCESSING UNITS  
A processor may include a plurality of processing units for processing instructions, where each processing unit is associated with a discrete instruction queue. Data is read from a data queue...
US20060004989 Mechanism for selecting instructions for execution in a multithreaded processor  
In one embodiment, a multithreaded processor includes a plurality of buffers, each configured to store instructions corresponding to a respective thread. The multithreaded processor also includes...
US20060212682 Processor utilizing novel architectural ordering scheme  
Various methods, apparatuses, and systems in which a processor includes an issue engine and an in-order execution pipeline. The issue engine categorizes operations as at least one of either a...
US20130305021 METHOD FOR CONVERGENCE ANALYSIS BASED ON THREAD VARIANCE ANALYSIS  
Basic blocks within a thread program are characterized for convergence based on variance analysis or corresponding instructions. Each basic block is marked as divergent based on transitive control...
US20080282067 Issue policy control within a multi-threaded in-order superscalar processor  
A multi-threaded in-order superscalar processor 2 includes an issue stage 12 including issue circuitry 22, 24 for selecting instructions to be issued to execution units 14, 16 in dependence upon a...
US20090024838 MECHANISM FOR SUPPRESSING INSTRUCTION REPLAY IN A PROCESSOR  
A mechanism for suppressing instruction replay includes a processor having one or more execution units and a scheduler that issue instruction operations for execution by the one or more execution...
US20090210664 System and Method for Issue Schema for a Cascaded Pipeline  
The present invention provides system and method for a group priority issue schema for a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having four or more...
US20100257336 Dependency Matrix with Reduced Area and Power Consumption  
A processor having a dependency matrix comprises a first array comprising a plurality of first cells. A second array couples to the first array and comprises a plurality of second cells. A first...
US20130013897 METHOD TO DYNAMICALLY DISTRIBUTE A MULTI-DIMENSIONAL WORK SET ACROSS A MULTI-CORE SYSTEM  
A method provides efficient dispatch/completion of an N Dimensional (ND) Range command in a data processing system (DPS). The method comprises: a compiler generating one or more commands from...
US20070028078 Instruction queues in pipelined processors  
A data processing apparatus comprising: a pipelined processor comprising an execution pipeline operable to execute instructions in a plurality of execution stages; a fetch unit for fetching...
US20090144526 SYSTEM AND METHOD OF ACCESSING A DEVICE  
A method of accessing a device is provided. A command is received from an agent, over a network, for executing at least one instruction for accessing the device. Information is sent to the agent,...
US20060200646 Data processing system with clustered ilp processor  
The invention is based on the idea to specify operations from different cycles in one instruction and, consequently, to pipeline control connections to remote clusters. Therefore a data processing...
US20070113053 MULTITHREADING INSTRUCTION SCHEDULER EMPLOYING THREAD GROUP PRIORITIES  
A concurrent instruction dispatch apparatus includes a group indicator for each of a plurality of threads that indicates which one of a plurality of groups of the threads the thread belongs to. A...
US20080133885 HIERARCHICAL MULTI-THREADING PROCESSOR  
A hierarchical microprocessor. An embodiment of a hierarchical microprocessor includes a plurality of first-level instruction pipeline elements; a plurality of execution clusters, where each...
US20060155963 Assist thread for injecting cache memory in a microprocessor  
A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system...
US20060090061 Continual flow processor pipeline  
Embodiments of the present invention relate to a system and method for comparatively increasing processor throughput and relieving pressure on the processor's scheduler and register file by...
US20090019262 PROCESSOR MICRO-ARCHITECTURE FOR COMPUTE, SAVE OR RESTORE MULTIPLE REGISTERS, DEVICES, SYSTEMS, METHODS AND PROCESSES OF MANUFACTURE  
An electronic circuit (4000) includes a bias value generator circuit (3900) operable to supply a varying bias value in a programmable range, and an instruction circuit (3625, 4010) responsive to a...
US20080168260 Symbolic Execution of Instructions on In-Order Processors  
A method is provided for processing instructions by a processor, in which instructions are queued in an instruction pipeline in a queued order. A first instruction is identified from the queued...
US20080122843 MULTI-THREAD VERTEX SHADER, GRAPHICS PROCESSING UNIT AND FLOW CONTROL METHOD  
A logic unit is provided for performing operations in multiple threads on vertex data. The logic unit comprises a macro instruction register file, a flow control instruction register file, and a...
US20140223144 Load Latency Speculation In An Out-Of-Order Computer Processor  
Load latency speculation in an out-of-order computer processor, including: issuing a load instruction for execution, wherein the load instruction has a predetermined expected execution latency;...
US20140223143 LOAD LATENCY SPECULATION IN AN OUT-OF-ORDER COMPUTER PROCESSOR  
Load latency speculation in an out-of-order computer processor, including: issuing a load instruction for execution, wherein the load instruction has a predetermined expected execution latency;...
US20090024837 System and Method for Language Specification  
Described are a system and method for language specification. The device may include (a) a processor running an operating system and (b) an image capturing device scanning an image. The operating...
US20070168649 Control of priority and instruction rates on a multithreaded processor  
A method and apparatus for controlling issue rate of instructions for an instruction thread to be executed by a processor is provided. The rate at which instructions are to be executed for an...
US20060095729 Multithreaded processor with multiple concurrent pipelines per thread  
A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of...
US20060004986 Data processing apparatus address range dependent parallelization of instructions  
A data processing apparatus has an instruction memory system arranged to output an instruction word addressed by an instruction address. An instruction execution unit, processes a plurality of...

Matches 51 - 100 out of 233 < 1 2 3 4 5 >