|
Match
|
Document |
Document Title |
|
|
US20090307467 |
Performing An Allreduce Operation On A Plurality Of Compute Nodes Of A Parallel Computer
Methods, apparatus, and products are disclosed for performing an allreduce operation on a plurality of compute nodes of a parallel computer. Each compute node includes at least two processing...
|
|
|
US20090249028 |
PROCESSOR WITH INTERNAL RASTER OF EXECUTION UNITS
The present invention relates to a processor that, as its main feature, has an internal raster of ALUs, with the help of which sequential programs are executed. The connections between the ALUs are...
|
|
|
US20090228683 |
PARALLEL DATA PROCESSING APPARATUS
A controller operable to control an array of processing elements comprises a retrieval unit operable to retrieve instruction items for each of a plurality of instructions streams, each instruction...
|
|
|
US20090210652 |
SIGNAL ROUTING IN PROCESSOR ARRAYS
There is provided a method for routing a plurality of signals in a processor array, the processor array comprising a plurality of processor elements interconnected by a network of switches, each...
|
|
|
US20090204788 |
Programmable pipeline array
Disclosed is an array of programmable data-processing cells configured as a plurality of cross-connected pipelines. An apparatus includes cells capable of performing data-processing functions...
|
|
|
US20090164752 |
PROCESSOR MEMORY SYSTEM
A data processor comprises a plurality of processing elements (PEs), with memory local to at least one of the processing elements, and a data packet-switched network interconnecting the processing...
|
|
|
US20090031103 |
MECHANISM FOR IMPLEMENTING A MICROCODE PATCH DURING FABRICATION
A patch apparatus in a microprocessor is provided. The patch apparatus includes a plurality of fuse banks and an array controller. The plurality of fuse banks is configured to store associated...
|
|
|
US20080307196 |
Integrated Processor Array, Instruction Sequencer And I/O Controller
A computer processor having an integrated instruction sequencer, array of processing engines, and I/O controller. The instruction sequencer sequences instructions from a host, and transfers these...
|
|
|
US20080282061 |
Array Type Operation Device
An array calculation device that includes a processor array composed of a plurality of processor elements having been assigned with orders, acquires an instruction in each cycle, generates, in each...
|
|
|
US20080229059 |
Message routing scheme
Each possessor node in an array of nodes has a respective local node address, and each local node address comprises a plurality of components having an order of addressing significance from most to...
|
|
|
US20080148010 |
SEMICONDUCTOR INTEGRATED CIRCUIT
The system design is facilitated by eliminating the increase in data transfer volume of the whole system. In order to facilitate the system design, there are provided an operation unit array, a...
|