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US20090193225 |
SYSTEM AND METHOD FOR APPLICATION SPECIFIC ARRAY PROCESSING
A processing architecture and methods therein for building application specific array processing utilizing a sequential data bus for control and data propagation. The methods of array processing...
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US20090158007 |
SCALEABLE ARRAY OF MICRO-ENGINES FOR WAVEFORM PROCESSING
A system for implementing waveform processing in a software defined radio (SDR) includes a scaleable array processor having a plurality of micro-engines (MEs) interconnected by a two dimensional...
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US20090146691 |
LOGIC CELL ARRAY AND BUS SYSTEM
A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for...
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US20090094436 |
ULTRA-SCALABLE SUPERCOMPUTER BASED ON MPU ARCHITECTURE
The invention provides an ultra-scalable supercomputer based on MPU architecture in achieving the well-balanced performance of hundreds of TFLOPS or PFLOPS range in applications. The supercomputer...
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US20090055624 |
CONTROL OF PROCESSING ELEMENTS IN PARALLEL PROCESSORS
The present invention relates to the control of an array of processing elements in a parallel processor using row and column select lines. For each column in the array, a column select line...
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US20080244221 |
EXPOSING SYSTEM TOPOLOGY TO THE EXECUTION ENVIRONMENT
Embodiments of apparatuses, methods, and systems for exposing system topology to an execution environment are disclosed. In one embodiment, an apparatus includes execution cores and resources on a...
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US20080209163 |
DATA PROCESSING SYSTEM WITH BACKPLANE AND PROCESSOR BOOKS CONFIGURABLE TO SUPPPRT BOTH TECHNICAL AND COMMERCIAL WORKLOADS
A processor book designed to support both commercial workloads and technical workloads based on a dynamic or static mechanism of reconfiguring the external wiring interconnect. The processor book...
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US20080195842 |
ARRAY-TYPE PROCESSOR
Occurrence and propagation of glitches caused by changing the path layout are suppressed, thereby reducing the power consumption. An array-type processor comprises a plurality of processor elements...
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US20080176750 |
SYSTEMS, DEVICES, AND METHODS FOR INTERCONNECTED PROCESSOR TOPOLOGY
An analog processor, for example a quantum processor may include a plurality of elongated qubits that are disposed with respect to one another such that each qubit may selectively be directly...
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US20080162872 |
DATA PROCESSING SYSTEM, METHOD AND INTERCONNECT FABRIC SUPPORTING HIGH BANDWIDTH COMMUNICATION BETWEEN NODES
A data processing system includes a first processing node and a second processing node. The first processing node includes a plurality of first processing units coupled to each other for...
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US20080148120 |
Storing multicore chip test data
An integrated chip architecture is provided which allows for efficiently testing multiple cores included in the integrated chip architecture and storing corresponding diagnosis data which include...
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US20080148009 |
PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS AND COMMUNICATION ELEMENTS
A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one...
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US20080133879 |
SIMD parallel processor with SIMD/SISD/row/column operation modes
Provided is a single instruction multiple data (SIMD) parallel processor including a plurality of processing units connected to one another. Each processing unit includes: an instruction register;...
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US20080109635 |
GENERAL PURPOSE ARRAY PROCESSING
General purpose array processing techniques including processing methods and apparatus. Processors may include parallel processing paths designed with reusable computational components such as...
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US20080104367 |
Collective Network For Computer Structures
A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction...
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US20080059762 |
Multi-sequence control for a data parallel system
The present invention is a data parallel system which is able to utilize a very high percentage of processing elements. In an embodiment, the data parallel system includes an array of processing...
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US20080059761 |
FAULT TOLERANT CELL ARRAY ARCHITECTURE
A data processing system containing a monolithic network of cells with sufficient redundancy provided through direct logical replacement of defective cells by spare cells to allow a large...
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US20080052490 |
Computational resource array
A sea of computational resources includes a number of computational resources, each of which is a member of one or more nearest neighbor pairings. Each nearest neighbor pairing has an upstream...
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US20080052491 |
Manifold Array Processor
An array processor includes processing elements ( 00, 01, 02, 03, 10, 11, 12, 13, 20, 21, 22, 23, 30, 31, 32, 33 ) arranged in clusters (e.g., 44, 46, 48, 50 ) to form a rectangular array ( 40 )....
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