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US20090320005 |
CONTROLLING PARALLELIZATION OF RECURSION USING PLUGGABLE POLICIES
A parallelism policy object provides a control parallelism interface whose implementation evaluates parallelism conditions that are left unspecified in the interface. User-defined and other...
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US20090287905 |
PROCESSOR PIPELINE ARCHITECTURE LOGIC STATE RETENTION SYSTEMS AND METHODS
A solution for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor...
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US20090249025 |
Serial Data Processing Circuit
A serial data processing circuit that realizes the same performance as that of the pipeline processing with low power consumption. First to fourth latch units receive, in parallel, data sets...
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US20090210651 |
SYSTEM AND METHOD FOR OBTAINING DATA IN A PIPELINED PROCESSOR
A pipelined processor including one or more units having storage locations not directly accessible by software instructions. The processor includes a load-store unit (LSU) in direct communication...
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US20090204787 |
Butterfly Physical Chip Floorplan to Allow an ILP Core Polymorphism Pairing
Improved techniques for executing instructions in a pipelined manner that may reduce stalls that occur when executing dependent instructions are provided. Stalls may be reduced by utilizing a...
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US20090164751 |
Method,system and apparatus for main memory access subsystem usage to different partitions in a socket with sub-socket partitioning
Embodiments enable sub-socket partitioning that facilitates access among a plurality of partitions to a shared resource. A round robin arbitration policy is to allow each partition, within a...
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US20090164747 |
Method,system and apparatus for memory address mapping for sub-socket partitioning
Sub-socket partitioning is enabled using embodiments of the present invention. In one aspect, the memory mapping is performed to isolate memory access for each of the partitions by assigning a...
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US20090113211 |
PROCESSING UNIT INCLUDING A WIRELESS MODULE AND METHOD THEREOF
A processing unit includes a processing core and a wireless module directly connected to the processing core, wherein the wireless module is for providing wireless communications to the processing...
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US20090113171 |
TPM DEVICE FOR MULTI-PROCESSOR SYSTEMS
In one embodiment, a computer system comprises at least a first computing cell and a second computing cell, each computing cell comprising at least one processor, at least one programmable trusted...
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US20090112563 |
Design Structure For Maintaining Memory Data Integrity In A Processor Integrated Circuit Using Cache Coherency Protocols
A design structure for a processor system may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may embody a...
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US20080313421 |
LOW POWER-CONSUMPTION DATA PROCESSOR
A low power-consumption data processor, wherein instruction decoding is performed on an instruction memory and an instruction register by an instruction decoding unit through an instruction bus,...
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US20080313114 |
SYSTEMS, METHODS, AND APPARATUS FOR RECURSIVE QUANTUM COMPUTING ALGORITHMS
A recursive approach to quantum computing employs an initial solution, determines intermediate solutions, evaluates the intermediate solutions and repeats using the intermediate solution, if the...
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US20080307193 |
Semiconductor integrated circuit
A semiconductor integrated circuit (chip) includes a primary TAP controller and a secondary TAP controller. The primary TAP controller interprets a bit string of n bits included in the group 1...
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US20080288728 |
MULTICORE WIRELESS AND MEDIA SIGNAL PROCESSOR (MSP)
A media signal processor (MSP) architecture is disclosed in this invention To address the shortcomings of conventional high performance processing units, the MSP architecture is designed using a...
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US20080270745 |
Hardware acceleration of a write-buffering software transactional memory
A method and apparatus for accelerating a software transactional memory (STM) system is described herein. Annotation field are associated with lines of a transactional memory. An annotation field...
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US20080215850 |
SYSTEMS, METHODS AND APPARATUS FOR LOCAL PROGRAMMING OF QUANTUM PROCESSOR ELEMENTS
Systems, methods and apparatus for a scalable quantum processor architecture. A quantum processor is locally programmable by providing a memory register with a signal embodying device control...
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US20080195839 |
Reconfigurable, Modular and Hierarchical Parallel Processor System
The invention concerns a method for managing resources of a modular processor system comprising the following steps of transmitting an instruction of a programme contained in a first machine with...
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US20080195841 |
Driving apparatus of display device and driving method thereof
Disclosed is a driving apparatus of a display device having a plurality of pixels. The driving apparatus includes a signal generator that generates a shutdown signal, first and second register...
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US20080195840 |
Identifying Messaging Completion on a Parallel Computer
Methods, parallel computers, and products are provided for identifying messaging completion on a parallel computer. The parallel computer includes a plurality of compute nodes, the compute nodes...
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US20080189512 |
Processor for executing switch and translate instructions requiring wide operands
A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of...
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US20080184007 |
Method and system to combine multiple register units within a microprocessor
A method and system to combine multiple register units within a microprocessor, such as, for example, a digital signal processor, are described. A first register unit and a second register unit are...
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US20080162870 |
Virtual Cluster Architecture And Method
Disclosed is a virtual cluster architecture and method. The virtual cluster architecture includes N virtual clusters, N register files, M sets of function units, a virtual cluster control switch,...
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US20080158375 |
Method and system for image pre-processing
An imaging architecture has a memory module to store raw images for the pre-processing stage. The raw image from the output of the pre-processing block may be compressed by a compressor before the...
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US20080155230 |
Method and System for Providing Simultaneous Transcoding of Multi-Media Data
A method and system for providing simultaneous transcoding of multi-media data are disclosed. For example, the method receives multi-media data in a first format. In turn, the method transmits the...
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US20080133880 |
Instruction Controlled Data Processing Device
The data processing device has a plurality of functional units and issues instructions in successive instruction cycles. Instructions of a first type are each intended for one functional unit at a...
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US20080126743 |
Reducing Stalls in a Processor Pipeline
Systems and methods are disclosed herein for processing instructions in a processor pipeline to reduce the number of stalls therein. In an exemplary embodiment, a processor pipeline comprises a...
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US20080109634 |
Credit-based activity regulation within a microprocessor
A technique to control power consumption within a microprocessor. More particularly, embodiments of the invention relate to a technique to control power and performance within one or more...
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US20080109633 |
PROGRAM PROCESSING DEVICE AND PROGRAM PROCESSING METHOD
A program processing device comprises a CPU for carrying out predetermined processing according to a program; an internal memory storing the program and data generated by the CPU by carrying out...
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US20080109614 |
Speculative data value usage
A data processing system 2 utilises a register renaming mechanism 10, 26 to rename architectural register specifiers to physical register specifiers to facilitate out-of-order processing. The...
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US20080104365 |
CONFIGURABLE PROCESSOR DESIGN APPARATUS AND DESIGN METHOD, LIBRARY OPTIMIZATION METHOD, PROCESSOR, AND FABRICATION METHOD FOR SEMICONDUCTOR DEVICE INCLUDING PROCESSOR
A design apparatus for designing a processor re-configurable for an application, includes an analysis unit that analyzes the content of a program to be executed by the processor; a hardware...
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US20080098200 |
TWO DIMENSIONAL ADDRESSING OF A MATRIX-VECTOR REGISTER ARRAY
A processor for processing matrix data. The processor includes M independent vector register files which are adapted to collectively store a matrix of L data elements. Each data element has B...
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US20080091917 |
Apparatus and method for directing micro architectural memory region accesses
In an embodiment, memory access requests for information stored within a system memory pass through an integrated circuit. The system memory may include a micro-architectural memory region to store...
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US20080040574 |
SUPER-RECONFIGURABLE FABRIC ARCHITECTURE (SURFA): A MULTI-FPGA PARALLEL PROCESSING ARCHITECTURE FOR COTS HYBRID COMPUTING FRAMEWORK
A field programmable gate array includes a virtual bus interface that receives a control word from a host processor over a standard I/O bus. A configurable very long instruction word (VLIW)...
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US20080010434 |
Transmission apparatus, reception apparatus, and transmission/reception method for same
A receiving station repeatedly performs decoding processing of data in a decoding processing portion, performs error detection of the decoding results, and transmits to a transmitting station an...
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