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US20150363352 PULSE-LATCH BASED BUS DESIGN FOR INCREASED BANDWIDTH  
A memory bus comprising a plurality of latches arranged sequentially between a source node and a destination node of a channel of the memory bus; and a pulse generator. The pulse generator is...
US20150363110 MEMORY CONFIGURATION FOR INTER-PROCESSOR COMMUNICATION IN AN MPSoC  
A method determines a configuration for inter-processor communication for a heterogeneous multi-processor system. The method determines at least one subgraph of a graph representing communication...
US20150347324 System and Method for Shared Memory for FPGA Based Applications  
A system for shared memory for field programmable gate array based application which includes a host computer, at least one field program gate array and a physical interface is disclosed. The host...
US20150347021 VERIFICATION OF SERIALIZATION OF STORAGE FRAMES WITHIN AN ADDRESS SPACE VIA MULTI-THREADED PROGRAMS  
A method, system, and computer program product to verify serialization of storage frames within an address space via multi-threaded programs is described. The method includes dynamically scaling a...
US20150339063 SYSTEM AND METHOD FOR EFFICIENT BUFFER MANAGEMENT FOR BANKED SHARED MEMORY DESIGNS  
A system and method for efficient buffer management for banked shared memory designs are provided. In one embodiment, a controller within the switch is configured to manage the buffering of the...
US20150325272 IN-MEMORY LIGHTWEIGHT COHERENCY  
A system includes a plurality of host processors and a plurality of HMC devices configured as a distributed shared memory for the host processors. An HMC device includes a plurality of integrated...
US20150317182 THREAD WAITING IN A MULTITHREADED PROCESSOR ARCHITECTURE  
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for thread waiting. One of the methods includes starting, by a first thread on a processing core, a...
US20150309943 MEMORY CONTROL UNIT AND DATA STORAGE DEVICE INCLUDING THE SAME  
A data storage device includes a storage memory device, a control unit suitable for generating a descriptor, which describes a work for controlling the storage memory device, and storing the...
US20150302904 ACCESSING MEMORY  
A disclosed example method involves performing simultaneous data accesses on at least first and second independently selectable logical sub-ranks to access first data via a wide internal data bus...
US20150301977 Distributed Termination for Flyby Memory Buses  
Methods and systems that perform distributed termination for shared signal buses on memory modules. Distributed termination improves signal quality and results in higher overall memory...
US20150301949 USING BROADCAST-BASED TLB SHARING TO REDUCE ADDRESS-TRANSLATION LATENCY IN A SHARED-MEMORY SYSTEM WITH OPTICAL INTERCONNECT  
The disclosed embodiments provide a system that uses broadcast-based TLB sharing to reduce address-translation latency in a shared-memory multiprocessor system with two or more nodes that are...
US20150301917 Memory Monitoring Method and Related Apparatus  
A memory monitoring method and a computing system. The computing system includes a processor, a memory and a monitor. The monitor obtains memory unit access information and process information of...
US20150301763 Storage Module and Method for Adaptive Burst Mode  
A storage module and method for adaptive burst mode are provided. In one embodiment, a storage module is provided comprising a memory and a controller. The controller is configured to receive a...
US20150293780 Method and System for Reconfigurable Virtual Single Processor Programming Model  
A non-transitory computer-readable storage medium storing a set of instructions that are executable by a processor. The set of instructions, when executed by one or more processors of a...
US20150293720 METHOD AND RELATED DEVICE FOR DETERMINING MANAGEMENT MODE OF SHARED VIRTUAL MEMORY PAGE  
A method and a related device for determining a management mode of a shared virtual memory page are disclosed. In one example, a method is disclosed that includes monitoring frequency or mode of...
US20150293706 System and Method for Managing Space Allocation within a File System  
A chassis management controller includes a root file system, a shared memory, a daemon process module, and an interposer library. The root file system includes a plurality of directories...
US20150286578 MEMORY AND PROCESS SHARING VIA INPUT/OUTPUT WITH VIRTUALIZATION  
Embodiments of the present invention provide an approach for memory and process sharing via input/output (I/O) with virtualization. Specifically, embodiments of the present invention provide a...
US20150286497 COALESCING MEMORY TRANSACTIONS  
A transactional memory system coalesces two outermost transactions in a transactional memory environment. A processor of the transactional memory system executes a first transaction begin...
US20150278095 DATA PROCESSING DEVICE  
A data processing device includes: data processing stages having a processing element, a stage memory and an event controller; and an inter-stage bus connecting the stages via an access point....
US20150277967 Enabling Maximum Concurrency In A Hybrid Transactional Memory System  
In an embodiment of a transactional memory system, an apparatus includes a processor and an execution logic to enable concurrent execution of at least one first software transaction of a first...
US20150269111 ASYNCHRONOUSLY PREFETCHING SHARABLE MEMORY PAGES  
When a process is swapped out of memory, a record of the sharable memory pages of the process is maintained. The sharable memory pages can then be repurposed. When the process is subsequently...
US20150269097 System and Method for Elastic Despreader Memory Management  
The disclosure is directed to a system and method of managing memory resources in a communication channel. According to various embodiments, incoming memory slices associated with a plurality of...
US20150261528 COMPUTER ACCELERATOR SYSTEM WITH IMPROVED EFFICIENCY  
A specialized memory access processor is placed between a main processor and accelerator hardware to handle memory access for the accelerator hardware. The architecture of the memory access...
US20150261472 MEMORY INTERFACE SUPPORTING BOTH ECC AND PER-BYTE DATA MASKING  
A memory and a method of storing data in a memory are provided. The memory comprises a memory block comprising data bits and additional bits. The memory includes logic which, when receiving a...
US20150254009 MEMORY SYSTEM  
A memory system according to the present embodiment includes a memory controller including a first data bus and a first address bus. A memory part includes a second data bus and a second address...
US20150227462 REGION IDENTIFYING OPERATION FOR IDENTIFYING A REGION OF A MEMORY ATTRIBUTE UNIT CORRESPONDING TO A TARGET MEMORY ADDRESS  
A data processing apparatus has a memory attribute unit having storage regions for storing attribute data for controlling access to a corresponding memory address range by processing circuitry. In...
US20150205735 System and Method of Sharing Memory by Arbitrating Through An Internal Data Bus  
One or more methods and systems of sharing an external memory between functional modules of an integrated circuit chip are presented. The invention provides a system and method of reducing the...
US20150186409 PORTABLE ELECTRONIC DEVICE, METHOD FOR SHARING FILE BETWEEN MULTIPLE OPERATING SYSTEMS, RECORDING MEDIUM AND COMPUTER PROGRAM PRODUCT  
A method for sharing a file between multiple operating systems on a probable electronic device is provided. The method includes the following steps: in a first operating system, a central...
US20150186269 MANAGING MEMORY  
Embodiments of the present disclosure provide a method and apparatus for managing memory. Embodiments of the present disclosure, is related to a method and apparatus for managing memory,...
US20150169454 PACKET TRANSFER SYSTEM AND METHOD FOR HIGH-PERFORMANCE NETWORK EQUIPMENT  
The present disclosure relates to a packet transfer system and method, which can greatly improve the efficiency of a packet transfer scheme using a memory pool technique. The packet transfer...
US20150169223 DYNAMIC PROCESSOR-MEMORY REVECTORING ARCHITECTURE  
A global navigation satellite system (GNSS) includes an efficient memory sharing architecture that provides additional search capacity by, e.g., sharing a portion of GNSS receiver processor memory...
US20150161062 METHOD, DEVICE AND COMPUTER PROGRAM FOR DYNAMIC CONTROL OF MEMORY ACCESS DISTANCES IN A NUMA TYPE SYSTEM  
The dynamic monitoring of distances, in particular of memory access distances, in a non-uniform memory access (NUMA) type system comprising a plurality of processors, and a local memory being...
US20150161058 Digital Signal Processing Data Transfer  
A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each...
US20150153966 MEMORY DEVICE FOR MULTIPLE PROCESSORS AND MEMORY SYSTEM HAVING THE SAME  
A memory device for multiple processors capable of processing a plurality of memory access requests and a memory system having the same are provided. The memory device includes one command and...
US20150149736 FAST RESTART OF APPLICATIONS USING SHARED MEMORY  
Technologies are described for restarting an application while maintaining data in memory (e.g., using shared memory). For example, shared memory can be associated with an application. The shared...
US20150149735 MEMORY SYSTEM  
Provided is a device for use in a memory module coupled to a host memory controller over a bus, comprising memory module control logic to generate a request signal to a host memory controller...
US20150143040 MEMORY DEVICE AND METHOD HAVING ON-BOARD PROCESSING LOGIC FOR FACILITATING INTERFACE WITH MULTIPLE PROCESSORS, AND COMPUTER SYSTEM USING SAME  
A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The...
US20150113215 READ TRAINING A MEMORY CONTROLLER  
Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band...
US20150095565 READ TRAINING A MEMORY CONTROLLER  
Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band...
US20150089163 Memory Controller For Selective Rank Or Subrank Access  
A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes...
US20150074344 ADAPTIVE MEMORY SYSTEM FOR ENHANCING THE PERFORMANCE OF AN EXTERNAL COMPUTING DEVICE  
An adaptive memory system is provided for improving the performance of an external computing device. The adaptive memory system includes a single controller, a first memory type (e.g., Static...
US20150058565 APPARATUS AND METHOD FOR COMPRESSION OF CONFIGURATION DATA  
An apparatus includes a device programmer, coupled to a plurality of semiconductor fuses disposed on a die, configured to program the plurality of semiconductor fuses with compressed configuration...
US20150058524 BIMODAL FUNCTIONALITY BETWEEN COHERENT LINK AND MEMORY EXPANSION  
Methods and apparatus relating to provide bimodal functionality between a coherent link and memory expansion are described. In one embodiment, a processor is coupled to one or more agents via a...
US20150058514 STORAGE DEVICE AND INFORMATION PROCESSING SYSTEM  
A storage device able to make a redundant write operation of unselected data unnecessary and able to optimize an arrangement of pages to a state having a high efficiency for rewriting, wherein the...
US20150052316 CENTRALIZED MEMORY ALLOCATION WITH WRITE POINTER DRIFT CORRECTION  
A system for writing data includes a memory, at least one memory controller and control logic. The memory stores data units. The memory controller receives a write request associated with a data...
US20150046661 Dynamic Address Negotiation for Shared Memory Regions in Heterogeneous Muliprocessor Systems  
Mobile computing devices may be configured to compile and execute portions of a general purpose software application in an auxiliary processor (e.g., a DSP) of a multiprocessor system by reading...
US20150039840 REMOTE MEMORY RING BUFFERS IN A CLUSTER OF DATA PROCESSING NODES  
A data processing node has an inter-node messaging module including a plurality of sets of registers each defining an instance of a GET/PUT context and a plurality of data processing cores each...
US20150039821 COMMUNICATION APPARATUS AND DATA PROCESSING METHOD  
A communication apparatus comprises a general-purpose memory, and a high-speed memory that allows higher-speed access than the general-purpose memory. Protocol processing is executed to packetize...
US20150032960 ELECTRONIC DEVICES HAVING SEMICONDUCTOR MEMORY UNITS AND METHOD OF FABRICATING THE SAME  
Electronic devices have a semiconductor memory unit including a magnetization compensation layer in a contact plug. One implementation of the semiconductor memory unit includes a variable...
US20150012714 Method and System for Multiple Processors to Share Memory  
A method and system for multiple processors to share memory are disclosed. The method includes that: at least one local interconnection network is set, each of which is connected with at least two...