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US20170153981 Using Shared Virtual Memory Resources for Performing Memory-Mapping  
Functionality is described herein for memory-mapping an information unit (such as a file) into virtual memory by associating shared virtual memory resources with the information unit. The...
US20170147513 MULTIPLE PROCESSOR ACCESS TO SHARED PROGRAM MEMORY  
A shared program memory and related components configured to distribute data from a memory block to multiple processors at the same time. An arbiter determines what processors are requesting data...
US20170147393 CACHE-EFFICIENT SYSTEM FOR TWO-PHASE PROCESSING  
A system provides determination of a first plurality of the plurality of data records assigned to a first processing unit, identification of a first record of the first plurality of data records,...
US20170147391 Context Switching for Computing Architecture Operating on Sequential Data  
A data stream processing unit (DPU) and methods for its use and programming are disclosed. A DPU includes a number of processing elements (PEs) arranged in a physical sequence. Each datum in the...
US20170139630 INFORMATION STORAGE DEVICE, INFORMATION STORAGE SYSTEM, AND INFORMATION STORAGE CONTROL PROGRAM  
An information storage device is a device that communicates over a network with another device that is used by another user different from an own user who uses an own device, and includes a...
US20170116132 SHARING AN ACCELERATOR CONTEXT ACROSS MULTIPLE PROCESSES  
The present disclosure relates to sharing a context on a coherent hardware accelerator among multiple processes. According to one embodiment, in response to a first process requesting to create a...
US20170115921 SHARING AN ACCELERATOR CONTEXT ACROSS MULTIPLE PROCESSES  
The present disclosure relates to sharing a context on a coherent hardware accelerator among multiple processes. According to one embodiment, in response to a first process requesting to create a...
US20170102892 PERFORMANCE OF COPROCESSOR ASSISTED MEMSET() THROUGH HETEROGENEOUS COMPUTING  
Techniques herein perform coprocessor assisted memory filling in a pipeline. A computer receives a request to fill multiple ranges of memory addresses with a value. The computer selects a first...
US20170090803 METHOD AND DEVICE FOR CHECKING FALSE SHARING IN DATA BLOCK DELETION  
Various embodiments of the present disclosure relates to a method and device for checking false sharing in deletion of a data block. The method includes setting weight bits and a weight reset bit...
US20170083257 On-chip Atomic Transaction Engine  
A hardware-assisted Distributed Memory System may include software configurable shared memory regions in the local memory of each of multiple processor cores. Accesses to these shared memory...
US20170060736 Dynamic Memory Sharing  
Methods and apparatuses pertaining to dynamic memory sharing may involve sharing a first portion of a memory associated with a first module for use by a second module. The first portion of the...
US20170031625 DATA COLLECTION IN A MULTI-THREADED PROCESSOR  
Data collection is facilitated by a multi-threaded processor. One thread of the processor obtains data placed in a buffer by another thread of the processor. The thread placing the data in the...
US20160306741 Data Migration Method and Apparatus, and Processor  
An on-chip memory in a many-core system is partitioned, and according to a frequency at which a processor core set in each on-chip partition accesses a virtual memory page in virtual memory space...
US20160299693 NATIVE STORAGE QUALITY OF SERVICE FOR VIRTUAL MACHINES  
Techniques to satisfy quality of service (QoS) requirements on a per virtual machine basis natively in a storage system are disclosed. In various embodiments, for each of a plurality of virtual...
US20160283158 ACCESSING GLOBAL DATA FROM ACCELERATOR DEVICES  
An aspect includes a table of contents (TOC) that was generated by a compiler being received at an accelerator device. The TOC includes an address of global data in a host memory space. The global...
US20160253098 SYSTEM AND METHOD OF A SHARED MEMORY HASH TABLE WITH NOTIFICATIONS  
A method and apparatus of a device that includes a shared memory hash table that notifies one or more readers of changes to the shared memory hash table is described. In an exemplary embodiment, a...
US20160246515 METHOD AND ARRANGEMENT FOR CONTROLLING REQUESTS TO A SHARED ELECTRONIC RESOURCE  
A method and a resource controller for controlling requests to a shared electronic resource, is described. The requests are arranged in the queue together with a counter which is set to a...
US20160239236 Methods And Apparatus Of Adaptive Memory Preparation  
A technique, as well as select implementations thereof, pertaining to adaptive memory preparation is described. The technique may involve analyzing memory usage data of a plurality of child...
US20160211973 METHOD AND APPARATUS FOR SCRAMBLING READ DATA IN A MEMORY MODULE  
Provided are a method and apparatus method and apparatus for scrambling read data in a memory module. A read data packet having scrambled read data returned in response to a read request is...
US20160188484 SYSTEM AND METHODS EXCHANGING DATA BETWEEN PROCESSORS THROUGH CONCURRENT SHARED MEMORY  
A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors...
US20160188382 SYSTEMS, APPARATUSES, AND METHODS FOR DATA SPECULATION EXECUTION  
Systems, methods, and apparatuses for data speculation execution (DSX) are described. In some embodiments, a hardware apparatus for performing DSX comprises a hardware decoder to decode an...
US20160179742 METHOD AND APPARATUS FOR PROVIDING A HOST MEMORY CONTROLLER WRITE CREDITS FOR WRITE COMMANDS  
Provided are a method and apparatus for providing a host memory controller write credits for write commands. A host memory controller coupled to a memory module over a bus determines whether a...
US20160179569 APPARATUS AND METHOD FOR A PROFILER FOR HARDWARE TRANSACTIONAL MEMORY PROGRAMS  
An apparatus and method are described for a hardware transactional memory (HTM) profiler. For example, one embodiment of an apparatus comprises a transactional debugger (TDB) recording module to...
US20160179427 LOW POWER ENTRY IN A SHARED MEMORY LINK  
Data is sent to correspond to a load/store-type operation associated with shared memory over a link according to a memory access link protocol and the memory access link protocol is to be overlaid...
US20160172271 Techniques for Interconnecting Stacked Dies Using Connection Sites  
An integrated circuit die includes conductive connection sites located at least on a surface of the integrated circuit die within a contiguous region thereof. The integrated circuit also includes...
US20160170917 DATA PROCESSING ARCHITECTURE AND DATA PROCESSING METHOD  
A data processing architecture includes a processor which may access a memory and fetch a command recorded in the memory, transmit the fetched command to a subject configured to perform an...
US20160170901 MIGRATION OF VIRTUAL MACHINES WITH SHARED MEMORY  
A system and method of migration of a VM sharing a memory region with another VM includes identifying, by an identification module, a plurality of VMs running on a source host machine, where the...
US20160154742 DYNAMIC PINNING OF VIRTUAL PAGES SHARED BETWEEN DIFFERENT TYPE PROCESSORS OF A HETEROGENEOUS COMPUTING PLATFORM  
A computer system may support one or more techniques to allow dynamic pinning of the memory pages accessed by a non-CPU device, such as a graphics processing unit (GPU). The non-CPU may support...
US20160149120 ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME  
This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and...
US20160132264 SYSTEMS, DEVICES, MEMORY CONTROLLERS, AND METHODS FOR CONTROLLING MEMORY  
Systems, devices, memory controllers, and methods for controlling memory are described. One such method includes activating a memory unit of a memory device; after activating the memory unit,...
US20160118442 ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME  
Provided is an electronic device including a switching element, wherein the switching element may include a first electrode, a second electrode, a switching layer interposed between the first and...
US20160105363 MEMORY SYSTEM FOR MULTIPLE CLIENTS  
Output is produced from a content addressable memory block. Bus select logic is configured to operate on data from a selected client bus from a plurality of client buses. Each client bus includes...
US20160098366 METHOD AND APPARATUS FOR ENCODING REGISTERS IN A MEMORY MODULE  
Provided are a method and apparatus for method and apparatus for encoding registers in a memory module. A mode register command is sent to the memory module over a bus, initialization of the...
US20160092353 ESTABLISHING COLD STORAGE POOLS FROM AGING MEMORY  
Systems and methods may provide for detecting a pending write operation directed to a target memory region and determining whether the target memory region satisfies a degradation condition in...
US20160085687 MEMORY MANAGEMENT COMPONENT  
A memory management component arranged to receive memory access transactions and provide memory management functionality therefor, and a method of providing memory management functionality within...
US20160057058 CPP BUS TRANSACTION VALUE HAVING A PAM/LAM SELECTION CODE FIELD  
Within a networking device, packet portions from multiple PDRSDs (Packet Data Receiving and Splitting Devices) are loaded into a single memory, so that the packet portions can later be processed...
US20160055119 Disaggregated Server Architecture for Data Centers  
A system comprising a unified interconnect network, a plurality of process memory modules, and a plurality of processor modules configured to share access to the memory modules via the unified...
US20160041943 MEMORY CIRCUIT CONFIGURATION SCHEMES ON MULTI-DROP BUSES  
Memory circuit configuration schemes on multi-drop buses are disclosed. In aspects disclosed herein, an on-die mapping logic is provided in a memory circuit. A memory controller communicates with...
US20160041923 Inter-Manycore Communications Method and System  
An inter-manycore communications method includes applying, by a service manager process, to a microkernel operating system for shared memory, and mapping shared memory, which is allocated by the...
US20160026598 STORAGE CONTROL DEVICES AND INVOKING METHOD THEREOF  
A storage control device comprises a storage control module and a memory module. The storage control module is coupled between a central processing unit and a plurality of hard disk drives. The...
US20160026567 DIRECT MEMORY ACCESS METHOD, SYSTEM AND HOST MODULE FOR VIRTUAL MACHINE  
The present disclosure provides a direct memory access method, system and host module for a virtual machine. The direct memory access method comprises the following steps. Firstly, a host virtual...
US20160004559 SOFTWARE ENABLED AND DISABLED COALESCING OF MEMORY TRANSACTIONS  
A program controls coalescing of outermost memory transactions, the coalescing causing committing of memory store data to memory for a first transaction to be done at transaction execution (TX)...
US20160004558 ALERTING HARDWARE TRANSACTIONS THAT ARE ABOUT TO RUN OUT OF SPACE  
A transactional memory system determines whether to pass control of a transaction to an about-to-run-out-of-resource handler. A processor of the transactional memory system determines information...
US20150378792 DEFERRAL INSTRUCTION FOR MANAGING TRANSACTIONAL ABORTS IN TRANSACTIONAL MEMORY COMPUTING ENVIRONMENTS  
A deferral instruction associated with a transaction is executed in a transaction execution computing environment with transactional memory. Based on executing the deferral instruction, a...
US20150378779 COLLECTING TRANSACTIONAL EXECUTION CHARACTERISTICS DURING TRANSACTIONAL EXECUTION  
Execution of a transaction may be initiated by a CPU in a transactional execution (TX) environment. A set of TX performance characteristics of the transaction during the transactional execution...
US20150378778 TRANSACTIONAL MEMORY OPERATIONS WITH WRITE-ONLY ATOMICITY  
Execution of a transaction mode setting instruction causes a computer processor to be in an atomic write-only mode ignoring conflicts to certain read-sets of a transaction during transactional...
US20150378777 TRANSACTIONAL MEMORY OPERATIONS WITH READ-ONLY ATOMICITY  
Execution of a transaction mode setting instruction causes a computer processor to be in an atomic read-only mode ignoring conflicts to certain write-sets of a transaction during transactional...
US20150370614 SUPPORTING ATOMIC ACCUMULATION WITH AN ADDRESSABLE ACCUMULATOR  
Atomically accumulating memory updates in a computer system configured with an accumulator that is memory mapped. The accumulator includes an accumulator memory and an accumulator queue and is...
US20150370586 LOCAL SERVICE CHAINING WITH VIRTUAL MACHINES AND VIRTUALIZED CONTAINERS IN SOFTWARE DEFINED NETWORKING  
Methods, software, and apparatus for implementing local service chaining (LSC) with virtual machines (VMs) or virtualized containers in Software Defined Networking (SDN). In one aspect a method is...
US20150370507 USING THE TRANSACTION-BEGIN INSTRUCTION TO MANAGE TRANSACTIONAL ABORTS IN TRANSACTIONAL MEMORY COMPUTING ENVIRONMENTS  
When executed, a transaction-begin instruction specifies an initial value for a transaction-count-to-completion (CTC) value for a transaction. The initial value indicates a predicted duration of...