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US20070174558 Method, system and program product for communicating among processes in a symmetric multi-processing cluster environment  
A facility is provided for communicating among processes in a symmetric multi-processing (SMP) cluster environment wherein at least some SMP nodes of the SMP cluster include multiple processes....
US20130111152 METHOD FOR OPTIMIZING MEMORY ACCESS IN A MICROPROCESSOR INCLUDING SEVERAL LOGIC CORES UPON RESUMPTION OF EXECUTING AN APPLICATION, AND COMPUTER PROGRAM IMPLEMENTING SUCH A METHOD  
The invention relates in particular to optimizing memory access in a microprocessor including several logic cores upon the resumption of executing a main application, and enabling the simultaneous...
US20050015568 Method and system of writing data in a multiple processor computer system  
A method and system for executing a first instance of a program on a first processor in computer system having multiple processors (wherein the program refers to a virtual memory address in a page...
US20080104245 System and method for selectively controlling the addition of reserve computing capacity  
In one embodiment, a system and method is disclosed for changing the resource availability of a particular user in a manner calculated to add the least cost to the user. A cluster of partition...
US20120221799 SYSTEMS AND METHODS FOR PERFORMING STORAGE OPERATIONS IN A COMPUTER NETWORK  
Methods and systems are described for performing storage operations on electronic data in a network. In response to the initiation of a storage operation and according to a first set of selection...
US20050246502 Dynamic memory mapping  
In at least some embodiments, a system comprises two processor cores, an external memory coupled to the two processor cores, and a program that is executable at least in part by one or both of the...
US20100205382 DYNAMIC QUEUE MANAGEMENT  
A method may include receiving a data unit and identifying a state of a memory storing data units. The method may include selecting a threshold value having a first threshold unit or a second...
US20130138929 PROCESS MAPPING IN PARALLEL COMPUTING  
A method of mapping processes to processors in a parallel computing environment where a parallel application is to be run on a cluster of nodes wherein at least one of the nodes has multiple...
US20100017569 PCB INCLUDING MULTIPLE CHIPS SHARING AN OFF-CHIP MEMORY, A METHOD OF ACCESSING OFF-CHIP MEMORY AND A MCM UTILIZING FEWER OFF-CHIP MEMORIES THAN CHIPS  
A PCB having fewer off-chip memories than chips, a MCM, and a method of accessing an off-chip shared memory space. In one embodiment, the method includes: (1) generating a memory request at a...
US20060206663 Disk array device and shared memory device thereof, and control program and control method of disk array device  
The disk array device realizing speed-up of cache control by the use of a high-speed throughput bus, which includes a director device having an external interface control unit, a data transfer...
US20150154045 CONTENTION MANAGEMENT FOR A HARDWARE TRANSACTIONAL MEMORY  
A hardware transactional memory is provided within a multiprocessor system with coherency control and hardware transaction memory control circuitry that serves to at least partially manage the...
US20100077156 PROCESSOR, PROCESSING SYSTEM, DATA SHARING PROCESSING METHOD, AND INTEGRATED CIRCUIT FOR DATA SHARING PROCESSING  
A processing device that processes data with use of one or more data blocks shared with a plurality of external processing devices. The device includes: a processor; a shared data storage unit...
US20140258643 METHOD AND SYSTEM FOR MAINTAINING RELEASE CONSISTENCY IN SHARED MEMORY PROGRAMMING  
A method and system for maintaining release consistency in shared memory programming on a computing device having multiple processing units includes, in response to a page fault, initiating a...
US20140006724 EFFICIENT MEMORY MANAGEMENT FOR PARALLEL SYNCHRONOUS COMPUTING SYSTEMS  
Technologies relating to efficient memory management for parallel synchronous computing systems are disclosed. Parallel synchronous computing systems may include, for example, a host, a memory...
US20080086603 Memory management method and system  
Systems, apparatuses and methods for efficient logical memory management using centralized memory management. One embodiment involves allocating a first memory region to a first subsystem,...
US20130282990 SHARED MEMORY ARCHITECTURE  
A shared memory architecture is disclosed to support operations associated with executing shared functions from a shared memory space in such a manner that separate pieces of software can execute...
US20110307669 SHARED MEMORY ARCHITECTURE  
A shared memory architecture is disclosed to support operations associated with executing shared functions from a shared memory space in such a manner that separate pieces of software can execute...
US20100174875 System and Method for Transactional Locking Using Reader-Lists  
In traditional transactional locking systems, such as TLRW, threads may frequently update lock metadata, causing system performance degradation. A system and method for implementing transactional...
US20080307276 Memory Controller with Loopback Test Interface  
In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller...
US20060282623 Systems and methods of accessing common registers in a multi-core processor  
Systems and methods for accessing common registers in a multi-core processor are disclosed. In an embodiment a method may comprise streaming at least one transaction from one of a plurality of...
US20090172299 System and Method for Implementing Hybrid Single-Compare-Single-Store Operations  
A hybrid Single-Compare-Single-Store (SCSS) operation may exploit best-effort hardware transactional memory (HTM) for good performance in the case that it succeeds, and may transparently resort to...
US20110214123 Mechanism for Optimal Placement of Virtual Machines to Reduce Memory Consumption Based on Shared Images  
A mechanism for optimal placement of VMs based on shared images is disclosed. A method of embodiments of the invention includes identifying a virtual machine (VM) image of a new VM to be placed by...
US20070239942 Transactional memory virtualization  
Methods and apparatus to provide transactional memory execution in a virtualized mode are described. In one embodiment, data corresponding to a transactional memory access request may be stored in...
US20090307434 METHOD FOR MEMORY INTERLEAVE SUPPORT WITH A CEILING MASK  
A distributed shared memory multiprocessor system that supports both fine- and coarse-grained interleaving of the shared memory address space. A ceiling mask sets a boundary between the fine-grain...
US20080244195 METHODS AND APPARATUSES TO SUPPORT MEMORY TRANSACTIONS USING PARTIAL PHYSICAL ADDRESSES  
Methods and apparatuses to support memory transactions using partial physical addresses are disclosed. Method embodiments generally comprise home agents monitoring multiple responses to multiple...
US20100250867 COMPUTER ARCHITECTURES USING SHARED STORAGE  
Shared storage architectures and methods are provided. A particular shared storage architecture is a system including shared storage including data and file system metadata separated from the...
US20090119463 SYSTEM AND ARTICLE OF MANUFACTURE FOR DUMPING DATA IN PROCESSING SYSTEMS TO A SHARED STORAGE  
Provided are a system and article of manufacture for dumping data in processing systems to a shared storage. A plurality of processing systems receive a signal indicating an event. Each of the...
US20110078385 System and Method for Performing Visible and Semi-Visible Read Operations In a Software Transactional Memory  
The software transactional memory system described herein may implement a revocable mechanism for managing read ownership in a shared memory. In this system, write ownership may be revoked by...
US20100318821 SCALABLE, DYNAMIC POWER MANAGEMENT SCHEME FOR SWITCHING ARCHITECTURES UTILIZING MULTIPLE BANKS  
According to one general aspect, a method may include receiving data from a network device. In some embodiments, the method may include writing the data to a memory bank that is part of a...
US20100228924 RESOURCE SHARING IN A TELECOMMUNICATIONS ENVIRONMENT  
A transceiver is designed to share memory and processing power amongst a plurality of transmitter and/or receiver latency paths, in a communications transceiver that carries or supports multiple...
US20090063780 DATA PROCESSING SYSTEM AND METHOD FOR MONITORING THE CACHE COHERENCE OF PROCESSING UNITS  
The present invention relates to a data processing system with a plurality of processing units (PU), a shared memory (M) for storing data from said processing units (PU) and an interconnect means...
US20100333095 Bulk Synchronization in Transactional Memory Systems  
A method and system for acquiring multiple software locks in bulk is disclosed. When multiple locks need to be acquired, such as for atomic transactions in transactional memory systems, the...
US20080098178 DATA STORAGE ON A SWITCHING SYSTEM COUPLING MULTIPLE PROCESSORS OF A COMPUTER SYSTEM  
A computing system is provided which includes a number of processing units, and a switching system coupled with each of the processing units. The switching system includes a memory. Each of the...
US20080077745 Data processing device  
A data processing device that does not depend on the type of data, has wide application range, and can reduce memory access in data transfer via a buffer arranged in a memory is provided. In a...
US20070271419 Memory administrating method  
A memory administrating method of administrating a memory divided into plural memory regions each of which consists of consecutive memory addresses, comprises steps of: acquiring a memory region...
US20090254698 MULTI PORT MEMORY DEVICE WITH SHARED MEMORY AREA USING LATCH TYPE MEMORY CELLS AND DRIVING METHOD  
A multiport semiconductor memory device includes; first and second port units respectively coupled to first and second processors, first and second dedicated memory area accessed by first and...
US20090043970 DEVICE HAVING SHARED MEMORY AND METHOD FOR PROVIDING ACCESS STATUS INFORMATION BY SHARED MEMORY  
A device having a shared memory and a method for providing access status information by the shared memory are disclosed. A digital processing device includes n processors and a shared memory. The...
US20100235588 SHARED INFORMATION DISTRIBUTING DEVICE, HOLDING DEVICE, CERTIFICATE AUTHORITY DEVICE, AND SYSTEM  
A distributing device for generating private information correctly even if shared information is destroyed or tampered with. A shared information distributing device for use in a system for...
US20090299492 Control of connecting apparatuses in information processing system  
In an information processing system, a first system control apparatus of a first information processing apparatus causes a first connecting apparatus to disconnect from the first shared storage...
US20110004733 Node Identification for Distributed Shared Memory System  
An example embodiment of the present invention provides processes relating to a connection/communication protocol and a memory-addressing scheme for a distributed shared memory system. In the...
US20090024803 Multipath accessible semiconductor memory device having shared register and method of operating thereof  
A semiconductor memory device for use in a multiprocessor system may be provided. A chip size may be controlled, and a design of circuit may be relatively simplified. The semiconductor memory...
US20130332677 SHARED PHYSICAL MEMORY PROTOCOL  
A computer implemented program product and data processing system for receiving data to a targeted logical partition. A computer locates buffer element in reliance on a connection status bit...
US20120317372 Efficient Communication of Producer/Consumer Buffer Status  
A mechanism is provided for efficient communication of producer/consumer buffer status. With the mechanism, devices in a data processing system notify each other of updates to head and tail...
US20120159088 Processing Quality-of-Service (QoS) Information of Memory Transactions  
Systems and methods for processing quality-of-service (QoS) information of memory transactions are described. In an embodiment, a method comprises receiving identification information and...
US20100257374 COMPUTER ARCHITECTURES USING SHARED STORAGE  
Shared storage architectures are provided. A particular shared storage architecture includes an Enterprise Service Bus (ESB) system. The ESB system includes shared storage including data and file...
US20090282198 SYSTEMS AND METHODS FOR OPTIMIZING BUFFER SHARING BETWEEN CACHE-INCOHERENT CORES  
According to at least some embodiments, systems and methods are provided for mapping, by a first processor, of a memory portion that is inaccessible to a second processor to at least a segment of...
US20120239886 DELAYED UPDATING OF SHARED DATA  
To provide delayed updating of shared data, a concept of dualistic sequence information is introduced. In the concept, if during local modification of data, a modification to the data is published...
US20110153958 NETWORK LOAD REDUCING METHOD AND NODE STRUCTURE FOR MULTIPROCESSOR SYSTEM WITH DISTRIBUTED MEMORY  
Provided are a network load reducing method and a node structure for a multiprocessor system with a distributed memory. The network load reducing method uses a multiprocessor system including a...
US20100106758 COMPUTING DISCRETE FOURIER TRANSFORMS  
A system described herein includes a selector component that receives input data that is desirably transformed by way of a Discrete Fourier Transform, wherein the selector component selects one of...
US20150169360 CODE OPTIMIZATION TO ENABLE AND DISABLE COALESCING OF MEMORY TRANSACTIONS  
A transactional memory system controls the coalescing of outermost memory transactions. The coalescing causing committing of memory store data to memory for a first transaction to be done at...