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US20050262311 Hierarchical processor architecture for video processing  
A system may include a memory, a number of low-level processors, and a control processor. The memory may store indicator data, other data that is described by the indicator data, and instructions....
US20060277371 System and method to instrument references to shared memory  
In some embodiments, the invention involves instrumentation of computer binary code and, more specifically, dynamically identifying shared memory accesses at runtime and instrumenting the shared...
US20090300450 PACKET RETRANSMISSION AND MEMORY SHARING  
Through the identification of different packet-types, packets can be handled based on an assigned packet handling identifier. This identifier can, for example, enable forwarding of...
US20090327610 Method and System for Conducting Intensive Multitask and Multiflow Calculation in Real-Time  
The system for conducting intensive multitask and multistream calculation in real time comprises a central processor core (SPP) for supporting the system software and comprising a control unit...
US20050093998 Digital camera with variable size delete buffer  
A digital camera and method that provide the ability to dynamically partition memory (both internal and removable) into memory dedicated for saved images and memory dedicated for deleted images....
US20100023702 Shared JAVA JAR files  
Techniques are disclosed for sharing programmatic modules among isolated virtual machines. A master JVM process loads data from a programmatic module, storing certain elements of that data into...
US20150261531 CONDITIONAL TRANSACTION END INSTRUCTION  
A Conditional Transaction End (CTEND) instruction is provided that allows a program executing in a nonconstrained transactional execution mode to inspect a storage location that is modified by...
US20070260822 Sharing Memory Resources of Wireless Portable Electronic Devices  
It is not uncommon for two or more wireless-enabled devices to spend most of their time in close proximity to one another. For example, a person may routinely carry a personal digital assistant...
US20110055829 Mechanism for Virtual Synchrony Total Order Messaging for Virtual Machines  
A mechanism for virtual synchrony total order messaging for virtual machines is disclosed. A method of embodiments of the invention includes receiving a request to reserve a block of memory in a...
US20140156953 Unified Optimistic and Pessimistic Concurrency Control for a Software Transactional Memory (STM) System  
A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a memory address referenced by a...
US20100095047 MULTI-CORE DEVICE WITH OPTIMIZED MEMORY CONFIGURATION  
A multi-core device for a piece of electronic equipment includes at least two cores arranged to execute different software portions stored on a memory means. At least one of these cores is...
US20090307435 Distributed Computing Utilizing Virtual Memory  
A method for distributed computing utilizing virtual memory is disclosed. The method can include identifying a first node to process an application, identifying paging space accessible to the...
US20140379999 DATA QUEUE HAVING AN UNLIMITED DEPTH  
A method for transferring messages from a producer element to a consumer element uses a memory shared between the producer element and the consumer element, and a hardware queue including several...
US20110087846 Accessing a Multi-Channel Memory System Having Non-Uniform Page Sizes  
A method includes predicting a memory access pattern of each master of a plurality of masters. The plurality of masters can access a multi-channel memory via a crossbar interconnect, where the...
US20100088687 Variable Length Code Table Clustering Method, and Method and Apparatus for Sharing Memory of Multi-Codec by Using the Variable Length Code Table Clustering Method  
Provided are a method and apparatus for sharing a memory of a multi-codec. For each of a plurality of codecs, the method and apparatus cluster a variable length code tree into a plurality of...
US20090144510 VM INTER-PROCESS COMMUNICATIONS  
A method for enabling inter-process communication between a first application and a second application, the first application running within a first context and the second application running...
US20070239944 Apparatus for performing storage virtualization  
The splitting of storage applications and functions into a control path (CP) component and a data path (DP) component is disclosed. Reads and writes may be handled primarily in the DP. The CP may...
US20120317399 Performing A Local Reduction Operation On A Parallel Computer  
A parallel computer including compute nodes, each including two reduction processing cores, a network write processing core, and a network read processing core, each processing core assigned an...
US20110258245 Performing A Local Reduction Operation On A Parallel Computer  
A parallel computer including compute nodes, each including two reduction processing cores, a network write processing core, and a network read processing core, each processing core assigned an...
US20080270710 APPARATUS, METHOD AND DATA PROCESSING ELEMENT FOR EFFICIENT PARALLEL PROCESSING OF MULTIMEDIA DATA  
Provided are an apparatus, a method, and a data processing element (DPE) for efficient parallel processing of multimedia data. The DPE includes: a memory routing unit (MRU) comprising a shared...
US20080065854 Method and apparatus for accessing physical memory belonging to virtual machines from a user level monitor  
A processing system may include a service operating system (OS) and a guest virtual machine (VM). The service OS may be a host OS or an OS in a service VM, for instance. The guest VM may have a...
US20100088471 FIELD DEVICE  
Disclosed is a field device comprising: a storage section to store shared data which is shared between user modules; an interface section to obtain trigger information to access the shared data,...
US20100005284 DEVICE HAVING SHARED MEMORY AND METHOD FOR TRANSFERRING CODE DATA  
The present invention relates to a device having a shared memory and a code data transmitting method. According to an embodiment of the present invention, the digital processing device can include...
US20080294851 METHOD, APPARATUS, COMPUTER PROGRAM PRODUCT, AND SYSTEM FOR MANAGEMENT OF SHARED MEMORY  
A system for providing management of shared memory for concurrent access is provided. The system includes a hardware element, a software element, and a memory that is accessible by the hardware...
US20110239219 PROTECTING SHARED RESOURCES USING SHARED MEMORY AND SOCKETS  
Shared memory and sockets are used to protect shared resources in an environment where multiple operating systems execute concurrently on the same hardware. Rather than using spinlocks for...
US20090138665 MEMORY CONTROLLER  
To provide a memory controller capable of flexibly dealing with the change in the form of use or operation state of a system, a memory controller (1100) includes bus interfaces (1200, 1210, 1220),...
US20070079077 System, method, and computer program product for shared memory queue  
In summary, one aspect of the present invention is directed to a method for a shared memory queue to support communicating between computer processes, such as an enqueuing process and a dequeuing...
US20080288730 Transactional Memory System Which Employs Thread Assists Using Address History Tables  
A computing system uses specialized “Set Associative Transaction Tables” and additional “Summary Transaction Tables” to speed the processing of common transactional memory conflict cases and those...
US20070192547 Programmable processing unit  
In general, in one aspect, the disclosure describes a processing unit that includes an input buffer to store data received by the processing unit, a memory, an arithmetic logic unit coupled to the...
US20090024802 NON-VOLATILE MEMORY SHARING SYSTEM FOR MULTIPLE PROCESSORS AND RELATED METHOD THEREOF  
A non-volatile memory sharing system is provided. The non-volatile memory sharing system includes a plurality of processors comprising at least a first processor and a second processor, a...
US20060010296 Memory compression  
Exemplary embodiments of the present invention comprise a method for compressing data for storage in memory. According to one embodiment, the method forms a set of values based on a monotonically...
US20090222630 MEMORY SHARE BY A PLURALITY OF PROCESSORS  
The present invention is directed to a method and a device for memory share by a plurality of processors. The portable terminal according to an embodiment of the present invention comprises a main...
US20110246724 System and Method for Providing Locale-Based Optimizations In a Transactional Memory  
The system and methods described herein may reduce read/write fence latencies and cache pressure related to STM metadata accesses. These techniques may leverage locality information (as reflected...
US20100083120 Storage System, Control Program and Storage System Conttrol Method  
There is provided a storage system including one or more LDEVs, one or more processors, a local memory or memories corresponding to the processor or processors, and a shared memory, which is...
US20130332678 SHARED PHYSICAL MEMORY PROTOCOL  
A computer implemented method for receiving data to a targeted logical partition. A computer locates buffer element in reliance on a connection status bit array. The computer copies control...
US20130036272 STORAGE ENGINE NODE FOR CLOUD-BASED STORAGE  
A system includes a storage engine node that includes a processor and a memory coupled to the processor. The memory stores a protocol mapper executable by the processor to convert storage access...
US20120179879 MECHANISMS FOR EFFICIENT INTRA-DIE/INTRA-CHIP COLLECTIVE MESSAGING  
Mechanism of efficient intra-die collective processing across the nodelets with separate shared memory coherency domains is provided. An integrated circuit die may include a hardware collective...
US20120079204 Cache with Multiple Access Pipelines  
Parallel pipelines are used to access a shared memory. The shared memory is accessed via a first pipeline by a processor to access cached data from the shared memory. The shared memory is accessed...
US20130151791 TRANSACTIONAL MEMORY CONFLICT MANAGEMENT  
A computing device initiates a transaction, corresponding to an application, which includes operations for accessing data stored in a shared memory and buffering alterations to the data as...
US20060088054 Resource sharing in a telecommunications environment  
A transceiver is designed to share memory and processing power amongst a plurality of transmitter and/or receiver latency paths, in a communications transceiver that carries or supports multiple...
US20120017029 SHARING MEMORY SPACES FOR ACCESS BY HARDWARE AND SOFTWARE IN A VIRTUAL MACHINE ENVIRONMENT  
Example methods, apparatus, and articles of manufacture to share memory spaces for access by hardware and software in a virtual machine environment are disclosed. A disclosed example method...
US20110264841 SHARING OF CLASS DATA AMONG VIRTUAL MACHINE APPLICATIONS RUNNING ON GUESTS IN VIRTUALIZED ENVIRONMENT USING MEMORY MANAGEMENT FACILITY  
A method, system and computer program product for sharing class data among virtual machine applications running on one or more guests in a virtualized environment. A control program in a virtual...
US20090216963 SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A SHARED MEMORY TRANSLATION FACILITY  
A system, method and computer program product for providing a shared memory translation facility. The method includes receiving a request for access to a memory address from a requestor at a...
US20130046938 QoS-Aware Scheduling  
In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for...
US20090235003 MEMORY CONTROL DEVICE AND MEMORY CONTROL METHOD  
Access requests issued from access circuits 30, 40 are arbitrated in an arbitration circuit 20 and are accessed to a storage device 10. On the other hand, access requests issued from the access...
US20090249105 Hardware Controlled Power Management of Shared Memories  
This invention manages power down and wakeup of shared memories in a multiprocessor system. A register for each shared memory has bits corresponding to each master. When a master wants to power...
US20120159083 Systems and Methods for Processing Memory Transactions  
Systems and methods for performing memory transactions are described. In an embodiment, a system comprises a processor configured to perform an action in response to a transaction indicative of a...
US20120137082 GLOBAL AND LOCAL COUNTS FOR EFFICIENT MEMORY PAGE PINNING IN A MULTIPROCESSOR SYSTEM  
Embodiments of the disclosure relate to the management of memory pages available for pin operations by groups of processors in a multiprocessor system to reduce cache contention and improve system...
US20090254715 VARIABLE PARTITIONED BLOCKS IN SHARED MEMORY  
A method and device for varying the size of partitioned areas of a shared memory is disclosed. The present invention resets the size of partitioned areas by expanding the size of a shared area...
US20060059318 Managing shared memory usage within a memory resource group infrastructure  
A method for allocating memory associated with a local shared memory segment to facilitate execution of a first process. The method includes automatically allocating memory associated with a first...