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US20050198443 Verification of memory accesses by distal clients by testing memory access by a proximate client  
Described herein are systems and methods for verification of memory accesses by distal clients by testing memory access by a proximate client. A proximate client is associated with a first...
US20080005491 MEMORY SHARING METHOD FOR SHARING SRAM IN AN SOC DEVICE  
A memory sharing method for at least a functional module and a target module is disclosed. The functional module includes at least a static random access memory (SRAM), the memory sharing method...
US20100180086 DATA STORAGE DEVICE DRIVER  
A method, system, and computer usable program product for an improved data storage device driver are provided in the illustrative embodiments. For managing an elevator queue, several requests are...
US20110113426 APPARATUSES FOR SWITCHING THE RUNNING OF A VIRTUAL MACHINE BETWEEN MULTIPLE COMPUTER DEVICES BELONGING TO THE SAME COMPUTER PLATFORM AND THE ASSOCIATED SWITCHING METHODS  
An apparatus for managing a running virtual machine on a desktop or laptop platform includes a first computer device, a second computer device and a shared memory. The first computer device has a...
US20070061521 Processor assignment in multi-processor systems  
In one embodiment, a method of assigning a plurality of processes to a plurality of processors in a multi-processor computer system comprises attaching a plurality of processes to a memory segment...
US20050177700 System for providing multiple window environments in a mobile computing system and method thereof  
Disclosed is a system for providing multiple window environments in a mobile computing system and a method thereof, which enables a user to conveniently and selectively use a window system...
US20080082622 Communication in a cluster system  
Methods, systems and computer program products to communicate between System On Chip (SOC) units in a cluster configuration are provided herein. A local SOC unit that includes a local controller...
US20120131285 LOCKING AND SIGNALING FOR IMPLEMENTING MESSAGING TRANSPORTS WITH SHARED MEMORY  
Disclosed are systems and methods for transporting data using shared memory comprising allocating, by one of a plurality of sender application, one or more pages, wherein the one or more pages are...
US20080244196 Method and apparatus for a unified storage system  
A unified storage system for executing a variety of types of storage control software using a single standardized hardware platform includes multiple storage control modules connected to storage...
US20130318309 VIRTUALIZED DATA STORAGE IN A NETWORK COMPUTING ENVIRONMENT  
Methods and systems for load balancing read/write requests of a virtualized storage system. In one embodiment, a storage system includes a plurality of physical storage devices and a storage...
US20080052455 Method and System for Mapping Disk Drives in a Shared Disk Cluster  
An information handling system may include a cluster. The cluster may comprise at least a first node and a second node. The first node may include a first shared disk mapping driver and a second...
US20080141060 FAULT TOLERANT COMPUTER  
A fault tolerant computer comprises a first unit, a second unit, a delay buffer and a delay time setting unit. The first unit executes a computer program in response to an input signal. The second...
US20080155202 Frame Transfer Method and Device  
In a frame transfer method and device by which an address space of a shared buffer can be effectively utilized without a reduction of the space even if an abnormal operation occurs in a management...
US20080177941 Method of managing memory in multiprocessor system on chip  
Provided is a method of managing memory in a multiprocessor system on chip (MPSoC). According to an aspect of the present invention, locality of memory can be reflected and restricted memory...
US20090019236 Data write/read auxiliary device and method for writing/reading data  
A data write/read auxiliary device and method for writing/reading data are provided. A data storage unit and a program storage unit are installed in the data write/read auxiliary device, wherein...
US20090193236 CONDITIONAL MEMORY ORDERING  
A system for conditional memory ordering implemented in a multiprocessor environment. A conditional memory ordering instruction executes locally using a release vector containing release numbers...
US20100100689 TRANSACTION PROCESSING IN TRANSACTIONAL MEMORY  
A transactional memory processing system provides for the integration of transactional memory concepts at the compiler-level into a higher-level traditional transaction processing system. Atomic...
US20070294487 Unified memory system  
The unified memory system includes: a memory accessed from a plurality of masters; a speculative access control section for issuing, in response to a first access request to the memory from a CPU...
US20100161939 PARALLEL PROCESSING METHOD AND SYSTEM, FOR INSTANCE FOR SUPPORTING EMBEDDED CLUSTER PLATFORMS, COMPUTER PROGRAM PRODUCT THEREFOR  
A multi-processing system-on-chip including a cluster of processors having respective CPUs is operated by: defining a master CPU within the respective CPUs to coordinate operation of said...
US20080091886 Dynamic Path Determination To An Address Concentrator  
Methods and apparatus provide for dynamically determining unit-AC paths between a plurality of processing units and a plurality of address concentrators. The unit-AC paths may be determined by...
US20090077324 METHODS AND SYSTEMS FOR EXCHANGING DATA  
A method for exchanging data between a producer and a consumer is provided. The method includes writing the data with the producer without blocking the consumer and without waiting for access to...
US20080256374 Sharing Non-Sharable Devices Between an Embedded Controller and A Processor in a Computer System  
System and method for sharing a device, e.g., non-volatile memory, between a host processor and a microcontroller. In response to system state change to a first state wherein the microcontroller...
US20080263285 Processor extensions for accelerating spectral band replication  
Enhancements to hardware architectures (e.g., a RISC processor or a DSP processor) to accelerate spectral band replication (SBR) processing are described. In some embodiments, instruction...
US20120215990 METHOD AND APPARATUS FOR SELECTING A NODE WHERE A SHARED MEMORY IS LOCATED IN A MULTI-NODE COMPUTING SYSTEM  
A method and an apparatus for selecting a node where a shared memory is located in a multi-node computing system are provided, improving the total access performance of the multi-node computing...
US20150113232 Storage And Retrieval Of High Importance Pages In An Active Memory Sharing Environment  
Using a set of non-volatile storage media and a virtual input/output system operating in a memory sharing environment, by: (i) estimating which non-volatile storage medium, of the set of...
US20150113231 Storage and Retrieval of High Importance Pages In An Active Memory Sharing Environment  
Using a set of non-volatile storage media and a virtual input/output system operating in a memory sharing environment, by: (i) estimating which non-volatile storage medium, of the set of...
US20070168621 Memory reduction technique for statistics accumulation and processing  
To provide a memory efficient method and system for statistical data accumulation and processing, data is divided into multiple data zones and divided into subgroups of memories. A separate memory...
US20120166736 STORAGE SYSTEM COMPRISING MULTIPLE STORAGE APPARATUSES WITH BOTH STORAGE VIRTUALIZATION FUNCTION AND CAPACITY VIRTUALIZATION FUNCTION  
A first virtual storage and a second virtual storage share an external LU (Logical Unit) inside an external storage. The first virtual storage comprises a first LU, which comprises multiple first...
US20100250863 PAGING PARTITION ARBITRATION OF PAGING DEVICES TO SHARED MEMORY PARTITIONS  
Disclosed is a computer implemented method, computer program product, and apparatus to establish at least one paging partition in a data processing system. The virtualization control point (VCP)...
US20090228164 Control System For A Electrical Vehicle  
A control system for controlling the functionality of an electrically powered vehicle is described. The control system comprises a plurality of control modules in electronic communication with...
US20060190689 Method of addressing data in a shared memory by means of an offset  
This invention relates to a first method of referencing a first number for data (29) to be stored and a second method of referencing a first address for data to be retrieved. Said data is shared...
US20150193266 TRANSACTIONAL MEMORY HAVING LOCAL CAM AND NFA RESOURCES  
An automaton hardware engine employs a transition table organized into 2n rows, where each row comprises a plurality of n-bit storage locations, and where each storage location can store at most...
US20140344527 DYNAMIC RECONFIGURATION OF APPLICATIONS ON A MULTI-PROCESSOR EMBEDDED SYSTEM  
A multiprocessor system and method for swapping applications executing on the multiprocessor system are disclosed. The plurality of applications may include a first application and a plurality of...
US20070226422 MULTI-MASTER SYSTEM AND DATA TRANSFER SYSTEM  
A multi-master system 101 includes: a memory controller 4 that executes access requests for accessing a memory 5 issued from masters 1 through 3; a master 1 that issues a write request for writing...
US20090144509 MEMEORY SHARING BETWEEN TWO PROCESSORS  
A wireless device includes a memory having a data port configured to facilitate access to the memory and at least two processing units which are configured to share the memory. The device also...
US20090287886 VIRTUAL COMPUTING MEMORY STACKING  
Virtual stacking is utilized in a virtual machine environment by receiving a data element for storage to a shared memory location and writing to the shared memory location. Writing to the shared...
US20090249106 Automatic Wakeup Handling on Access in Shared Memory Controller  
A hardware based wake-up scheme initiates memory power-up upon a normal access to a powered down memory. The access that triggered the power-up is buffered. Further accesses are stalled until the...
US20140075128 RESOURCE SHARING IN A TELECOMMUNICATIONS ENVIRONMENT  
A transceiver is designed to share memory and processing power amongst a plurality of transmitter and/or receiver latency paths, in a communications transceiver that carries or supports multiple...
US20120297148 RESOURCE SHARING IN A TELECOMMUNICATIONS ENVIRONMENT  
A transceiver is designed to share memory and processing power amongst a plurality of transmitter and/or receiver latency paths, in a communications transceiver that carries or supports multiple...
US20080282042 Multi-path accessible semiconductor memory device with prevention of pre-charge skip  
A multiprocessor system includes first and second processors and a multi-path accessible semiconductor memory device including a shared memory area and a pseudo operation execution unit. The...
US20150081985 ADMINISTERING INTER-CORE COMMUNICATION VIA SHARED MEMORY  
Administering inter-core communication via shared memory may be carried out in a system in which each core is associated with a mailbox in a shared memory region. Such administration may include...
US20110179231 SYSTEM AND METHOD FOR CONTROLLING ACCESS TO SHARED STORAGE DEVICE  
A system and method for controlling access to a shared storage device in a computing cluster having at least two nodes configured as cluster members provide fencing and quorum features without...
US20120185725 COMPUTER ARCHITECTURES USING SHARED STORAGE  
A method includes providing a persistent common view of a virtual shared storage system. The virtual shared storage system includes a first shared storage system and a second shared storage...
US20100076944 MULTIPROCESSOR SYSTEMS FOR PROCESSING MULTIMEDIA DATA AND METHODS THEREOF  
A method and system for processing multimedia data is provided. The method for processing multimedia data in a multiprocessor system includes enabling communication between a plurality of...
US20150254191 Software Enabled Network Storage Accelerator (SENSA) - Embedded Buffer for Internal Data Transactions  
An apparatus and method of bypassing server DRAM by redirecting internal data transactions to an embedded buffer provides an innovative implementation for intermediate storage for internal...
US20150052287 NUMA Scheduling Using Inter-vCPU Memory Access Estimation  
In a system having non-uniform memory access architecture, with a plurality of nodes, memory access by entities such as virtual CPUs is estimated by invalidating a selected sub-set of memory...
US20130246714 SYSTEM AND METHOD FOR SUPPORTING BUFFER ALLOCATION IN A SHARED MEMORY QUEUE  
A system and method can support buffer allocation in a shared memory queue. The shared memory queue can be associated with a shared memory, to which one or more communication peers are attached....
US20090327617 Shared Object Control  
Methods, systems, and computer program products for controlling information read/write processing. The method includes assigning a plurality of division areas to a shared storage area for storing...
US20140244944 WAIT-FREE ALGORITHM FOR INTER-CORE, INTER-PROCESS, OR INTER-TASK COMMUNICATION  
A method and system are presented for providing deterministic inter-core, inter-process, and inter-thread communication between a reader and a writer. The reader and writer communicate by passing...
US20080016287 SYMBOL RATE HARDWARE ACCELERATOR  
A hardware accelerator includes a first buffer, a second buffer, address generator(s), a translation read-only memory (ROM), a cyclic redundancy check (CRC) generator, a convolutional encoder and...