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US20130246690 INFORMATION PROCESSING SYSTEM AND DATA-STORAGE CONTROL METHOD  
In an information processing system, a processor requests a first transfer control circuit to transfer data to a first memory. In response to the request from the processor, the first transfer...
US20130238862 FAST PREDICTION OF SHARED MEMORY ACCESS PATTERN  
A computer implemented method analyzes shared memory accesses during execution of an application program. The method includes instrumenting events of shared memory accesses in the application...
US20130219130 METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR INTER-CORE COMMUNICATION IN MULTI-CORE PROCESSORS  
Method, apparatus, and computer program product embodiments of the invention are disclosed for efficient communication between processor units in a multi-core processor integrated circuit...
US20130212338 MULTICORE PROCESSOR  
A multicore processor includes a plurality of cores; a shared memory that is shared by the cores and that is divided into a plurality of storage areas whose writable data sizes are determined in...
US20130185486 STORAGE DEVICE, STORAGE SYSTEM, AND INPUT/OUTPUT CONTROL METHOD PERFORMED IN STORAGE DEVICE  
A storage device includes a storage unit including a plurality of regions in which data is stored, the storage unit configured to input and output the data through channels and ways corresponding...
US20130166849 Physically Remote Shared Computer Memory  
A computing system with physically remote shared computer memory, the computing system including: a remote memory management module, a plurality of computing devices, a plurality of remote memory...
US20130151793 Multi-Context Configurable Memory Controller  
The exemplary embodiments provide a multi-context configurable memory controller comprising: an input-output data port array comprising a plurality of input queues and a plurality of output...
US20130151792 PROCESSOR COMMUNICATIONS  
A processor module including a processor configured to share data with at least one further processor module processor; and a memory mapped peripheral configured to communicate with at least one...
US20130145105 Data Storage Systems and Methods  
Example data storage systems and methods are described. In one implementation, a method identifies data to be written to a shared storage system that includes multiple storage nodes. The method...
US20130138885 DYNAMIC PROCESS/OBJECT SCOPED MEMORY AFFINITY ADJUSTER  
An apparatus, method, and program product for optimizing a multiprocessor computing system by sampling memory reference latencies and adjusting components of the system in response thereto. During...
US20130132684 AUTOMATIC OPTIMIZATION FOR PROGRAMMING OF MANY-CORE ARCHITECTURES  
The present invention extends to methods, systems, and computer program products for automatically optimizing memory accesses by kernel functions executing on parallel accelerator processors. A...
US20130124804 DATA RESTORATION PROGRAM, DATA RESTORATION APPARATUS, AND DATA RESTORATION METHOD  
A computer-readable recording medium stores a program that causes a computer capable of accessing a multicore processor equipped with volatile memories and a plurality of cores accessing the...
US20130117602 SEMICONDUCTOR MEMORY DEVICE AND SYSTEM HAVING REDUNDANCY CELLS  
In one embodiment, the memory device includes a memory cell array having at least a first memory cell group, a second memory cell group and a redundancy memory cell group. The first memory cell...
US20130111122 Method and apparatus for network table lookups  
An apparatus comprising a plurality of memory components each comprising a plurality of memory banks, a memory controller coupled to the memory components and configured to control and select a...
US20130097389 MEMORY ACCESS CONTROLLER, MULTI-CORE PROCESSOR SYSTEM, MEMORY ACCESS CONTROL METHOD, AND COMPUTER PRODUCT  
A memory access controller includes a semiconductor circuit configured to classify into a first group of cores having made an exclusive access request to shared memory and a second group of cores...
US20130097388 DEVICE AND DATA PROCESSING SYSTEM  
A device is disclosed which includes a register storing a plurality of latency data and a control unit responding to the latency data. Each of the latency data indicates a period of time between...
US20130091328 STORAGE SYSTEM  
A storage system in an embodiment of this invention comprises a non-volatile storage area for storing write data from a host, a cache area capable of temporarily storing the write data before...
US20130080710 HARDWARE METHOD FOR DETECTING TIMEOUT CONDITIONS IN A LARGE NUMBER OF DATA CONNECTIONS  
Tracking several open data connections is difficult with a large number of connections. Checking for timeouts in software uses valuable processor resources. Employing a co-processor dedicated to...
US20130073810 Memory Sharing Between Embedded Controller and Central Processing Unit Chipset  
An embedded controller includes a microcontroller core and memory control circuitry. The memory control circuitry is configured to communicate with a Central Processing Unit (CPU) chipset over a...
US20130042079 METHOD FOR PROCESSING DATA OF A CONTROL UNIT IN A DATA COMMUNICATION DEVICE  
A method for processing data of a control unit in a data communication device, which has a first memory area and a second memory area, and is connected to the control unit through an interface....
US20130013868 RING BUFFER  
A computer implemented method for writing to a software bound ring buffer. A network adapter may determine that data is available to write to the software bound ring buffer. The network adapter...
US20120331240 DATA PROCESSING DEVICE AND DATA PROCESSING ARRANGEMENT  
A data processing device is described with a memory and a first and a second data processing component. The first data processing component comprises a control memory comprising, for each memory...
US20120331239 SHARED MEMORY ARCHITECTURE  
Disclosed herein is an apparatus which may comprise a plurality of nodes. In one example embodiment, each of the plurality of nodes may include one or more central processing units (CPUs), a...
US20120317371 Usage Aware NUMA Process Scheduling  
Processes may be assigned to specific processors when memory objects consumed by the processes are located in memory banks closely associated with the processors. When assigning processes to...
US20120260046 PROGRAMMABLE LOGIC APPARATUS EMPLOYING SHARED MEMORY, VITAL PROCESSOR AND NON-VITAL COMMUNICATIONS PROCESSOR, AND SYSTEM INCLUDING THE SAME  
A programmable logic apparatus includes a shared memory having a first port, a second port and a third port; a first vital processor interfaced to the first port of the shared memory; and a...
US20120233409 MANAGING SHARED MEMORY USED BY COMPUTE NODES  
A technology can be provided for managing shared memory used by a plurality of compute nodes. An example system can include a shared globally addressable memory to enable access to shared data by...
US20120221795 SHARED MEMORY SYSTEM AND CONTROL METHOD THEREFOR  
A shared memory system provides an access monitoring mechanism 112 with a definition for taking clusters for motion picture attributes as pieces of cluster memory 1 and 2. When a DSP (2) 104 makes...
US20120166737 Information Processing Apparatus, Data Duplication Method, Program, and Storage Medium  
An enhanced security protection in data duplication using a shared storage area is provided. Specifically, an information processing apparatus, in which one or more applications operate, includes...
US20120144122 METHOD AND APPARATUS FOR ACCELERATED SHARED DATA MIGRATION  
A method and apparatus for accelerated shared data migration between cores is disclosed.
US20120110272 CROSS PROCESS MEMORY MANAGEMENT  
A method for efficiently managing memory resources in a computer system having a graphics processing unit that runs several processes simultaneously on the same computer system includes using...
US20120102274 MEMORY MANAGING APPARATUS, MULTIPROCESSOR SYSTEM, AND METHOD FOR CAUSING MEMORY MANAGING APPARATUS TO MANAGE SHARED MEMORY  
A memory managing apparatus manages a memory shared by processors. The apparatus includes an allocator, an updater and a releaser. The allocator secures a memory area in the memory allocated to...
US20120072676 SELECTIVE MEMORY COMPRESSION FOR MULTI-THREADED APPLICATIONS  
A method, system, and computer usable program product for selective memory compression for multi-threaded applications are provided in the illustrative embodiments. An identification of a memory...
US20120047390 APPARATUS AND METHOD OF CONTROLLING A PROCESSOR CLOCK FREQUENCY  
An apparatus and a method of controlling a processor clock frequency are provided. The apparatus comprises a hardware counter to count write accesses to a memory buffer during a predetermined...
US20120030433 Method, Mobile Terminal and Computer Program Product for Sharing Storage Device  
The invention discloses a method of sharing a storage device and a mobile terminal. The mobile terminal comprises a first processor, a second processor and a readable and writable nonvolatile...
US20120023296 Recording Dirty Information in Software Distributed Shared Memory Systems  
A page table entry dirty bit system may be utilized to record dirty information for a software distributed shared memory system. In some embodiments, this may improve performance without...
US20120005434 SEMICONDUCTOR MEMORY APPARATUS  
A semiconductor memory apparatus includes a data selection unit, a first data processing unit, and a second data processing unit. The data selection unit is configured to select one of the first...
US20120005401 PAGE BUFFERING IN A VIRTUALIZED, MEMORY SHARING CONFIGURATION  
An apparatus includes a processor and a volatile memory that is configured to be accessible in an active memory sharing configuration. The apparatus includes a machine-readable encoded with...
US20110320719 PROPAGATING SHARED STATE CHANGES TO MULTIPLE THREADS WITHIN A MULTITHREADED PROCESSING ENVIRONMENT  
A circuit arrangement and method make state changes to shared state data in a highly multithreaded environment by propagating or streaming the changes to multiple parallel hardware threads of...
US20110314338 DATA COLLISIONS IN CONCURRENT PROGRAMS  
Described are techniques for detecting data collisions between a first portion and a second portion of an application executing on a computer, the first portion and the second portions executing...
US20110307665 PERSISTENT MEMORY FOR PROCESSOR MAIN MEMORY  
Subject matter disclosed herein relates to a system of one or more processors that includes persistent memory.
US20110271060 Method And System For Lockless Interprocessor Communication  
A computer readable storage medium storing a set of instructions executable by a processor. The set of instructions is operable to receive, from a first processor, a message to be sent to a second...
US20110264867 MULTIPROCESSOR COMPUTING SYSTEM WITH MULTI-MODE MEMORY CONSISTENCY PROTECTION  
Disclosed are a method and apparatus for protecting memory consistency in a multiprocessor computing system, relating to program code conversion such as dynamic binary translation. The exemplary...
US20110252200 COHERENT MEMORY SCHEME FOR HETEROGENEOUS PROCESSORS  
Systems, methods, and devices for maintaining cache coherence between two or more heterogeneous processors are provided. In accordance with one embodiment, such an electronic device may include...
US20110246727 System and Method for Tracking References to Shared Objects Using Byte-Addressable Per-Thread Reference Counters  
The system described herein may track references to a shared object by concurrently executing threads using a reference tracking data structure that includes an owner field and an array of...
US20110246726 PROCESSING DATA IN SHARED MEMORY  
Various embodiments of systems and methods for processing data in shared memory are described herein. A number of work processes of an application server write data in corresponding areas of...
US20110239003 Direct Injection of Data To Be Transferred In A Hybrid Computing Environment  
Direct injection of a data to be transferred in a hybrid computing environment that includes a host computer and a plurality of accelerators, the host computer and the accelerators adapted to one...
US20110231616 DATA PROCESSING METHOD AND SYSTEM  
A configurable multi-core structure is provided for executing a program. The configurable multi-core structure includes a plurality of processor cores and a plurality of configurable local memory...
US20110213936 PROCESSOR, MULTIPROCESSOR SYSTEM, AND METHOD OF DETECTING ILLEGAL MEMORY ACCESS  
A processor included in a multiprocessor system including a shared memory, the processor according to an embodiment of the present invention comprises: a storing unit that stores a break...
US20110209151 AUTOMATIC SUSPEND AND RESUME IN HARDWARE TRANSACTIONAL MEMORY  
An apparatus and method is disclosed for a computer processor configured to access a memory shared by a plurality of processing cores and to execute a plurality of memory access operations in a...
US20110208921 INVERTED DEFAULT SEMANTICS FOR IN-SPECULATIVE-REGION MEMORY ACCESSES  
A method for accessing memory by a first processor of a plurality of processors in a multi-processor system includes, responsive to a memory access instruction within a speculative region of a...