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US20150006826 STRAP-BASED MULTIPLEXING SCHEME FOR MEMORY CONTROL MODULE  
Embodiments include integrated circuits (ICs), system-on-chips (SoCs), and related methods for a strap-based multiplexing scheme for a memory control module. In one embodiment, a memory control...
US20140359231 System and Method for Efficient Buffer Management for Banked Shared Memory Designs  
A system and method for system and method for efficient buffer management for banked shared memory designs. In one embodiment, a controller within the switch is configured to manage the buffering...
US20140351525 Efficient method for memory accesses in a multi-core processor  
A method of providing memory accesses for a multi-core processor includes reserving a group of pins of a multi-core processor to transmit either data or address information in communication with...
US20140331014 Scalable Matrix Multiplication in a Shared Memory System  
High performance computing systems perform complex or data-intensive calculations using a large number of computing nodes and a shared memory. Disclosed methods and systems provide nodes having a...
US20140304481 INFORMATION PROCESSING SYSTEM, CONTROL METHOD, PROGRAM, AND RECORDING MEDIUM  
An information processing system that determines whether static data is already loaded into shared memory when a request is made to load static data into shared memory from a process out of a...
US20140297968 MAGNETIC TUNNELING JUNCTION DEVICES, MEMORIES, MEMORY SYSTEMS, AND ELECTRONIC DEVICES  
Provided is a magnetic tunneling junction device including a first structure including a magnetic layer; a second structure including at least two extrinsic perpendicular magnetization structures,...
US20140297920 MULTI-CORE PROCESSOR AND CONTROL METHOD  
According to an embodiment, a multi-core processor is capable of executing a plurality of tasks. The multi-core processor includes at least a first core and a second core. The first core and the...
US20140281279 NONVOLATILE MEMORY DEVICE AND DATA MANAGEMENT METHOD THEREOF  
A data management method of a nonvolatile memory device which includes a data cell area and a reference cell area includes selecting shared data from write data input to the memory device;...
US20140281278 APPARATUS AND METHODS FOR A DISTRIBUTED MEMORY SYSTEM INCLUDING MEMORY NODES  
Apparatuses and methods for a distributed memory system including memory nodes are disclosed. An example apparatus includes a processor and a memory system coupled to the processor. The memory...
US20140281200 MEMORY DEVICES AND SYSTEMS INCLUDING MULTI-SPEED ACCESS OF MEMORY MODULES  
A system, comprising: a plurality of modules, each module comprising a plurality of integrated circuits devices coupled to a module bus and a channel interface that communicates with a memory...
US20140281178 METHOD FOR ASSIGNING ADDRESSES TO MEMORY DEVICES  
A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an array of memory cells, addressing...
US20140258626 ELECTRONIC DEVICES HAVING SEMICONDUCTOR MEMORY UNIT  
An electronic device includes: a variable resistance element having a first electrode, a variable resistance layer, and a second electrode which are sequentially stacked therein; a spacer formed...
US20140229686 Mixed Shared/Non-Shared Memory Transport for Virtual Machines  
Methods, systems and computer program products are provided for mixed shared/non-shared memory transport in virtual machines. A computer-implemented method may include providing a shared memory...
US20140223112 SYSTEM AND METHOD FOR MANAGING DATA ELEMENTS  
Systems and methods for managing data elements on a mobile device that involve identifying a central application with an available set of data elements, for each of a plurality of secondary...
US20140201470 SHARED OP-SYMMETRIC UPDATE-SENSITIVE VARIABLES  
Embodiments include multi-processor systems, including multi-core processor systems, as well as methods for operating the same, in which at least one processor or processor core is configured to...
US20140201469 SHARED OP-SYMMETRIC UPDATE-SENSITIVE VARIABLES  
Embodiments include multi-processor systems, including multi-core processor systems, as well as methods for operating the same, in which at least one processor or processor core is configured to...
US20140195742 SYSTEM ON CHIP INCLUDING MEMORY MANAGEMENT UNIT AND MEMORY ADDRESS TRANSLATION METHOD THEREOF  
A system on chip (SoC) including a memory management unit (MMU) and a memory address translation method thereof are provided. The SoC includes a master intellectual property (IP) configured to...
US20140195741 TYPE CASTING IN A MANAGED CODE SYSTEM  
Type casting in a managed code system is described. The managed code system includes managed memory as well as shared memory located outside of the managed memory. The managed memory has multiple...
US20140189259 SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE  
A semiconductor device includes a first memory controller configured to output a first control signal to first and second external memories through a first memory interface, a second memory...
US20140189258 SEMICONDUCTOR MEMORY DEVICE  
A semiconductor memory device includes a memory array including memory blocks stacked in a plurality of layers over a substrate, first lines coupling word lines of memory blocks arranged in...
US20140189257 SEMICONDUCTOR MEMORY DEVICE  
A semiconductor memory device includes stacked memory strings in which at least some adjacent memory strings share a common source line. During a read operation for a selected memory string, a...
US20140189256 PROCESSOR WITH MEMORY RACE RECORDER TO RECORD THREAD INTERLEAVINGS IN MULTI-THREADED SOFTWARE  
A processor includes a first core to execute a first software thread, a second core to execute a second software thread, and shared memory access monitoring and recording logic. The logic includes...
US20140149691 DATA PROCESSING SYSTEM AND DATA PROCESSING METHOD  
A data processing system includes multiple data processing apparatuses; a peripheral apparatus; memory that is shared by the data processing apparatuses and the peripheral apparatus; peripheral...
US20140143509 METHOD AND DEVICE FOR DATA PROCESSING  
The present provides a method for operating a module by a processor. The method includes generating, by at least one task being executed on the processor, control information for controlling...
US20140143508 MEMORY SYSTEM AND OPERATING METHOD THEREOF  
A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory dies having different page sizes. The memory controller generates a plurality of...
US20140136798 TRANSACTIONAL MEMORY THAT PERFORMS A PMM 32-BIT LOOKUP OPERATION  
A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a memory address. In response to the command, the TM pulls an input value (IV). The memory...
US20140129783 SYSTEM AND METHOD FOR ALLOCATING MEMORY OF DIFFERING PROPERTIES TO SHARED DATA OBJECTS  
A system and method for allocating shared memory of differing properties to shared data objects and a hybrid stack data structure. In one embodiment, the system includes: (1) a hybrid stack...
US20140122801 MEMORY CONTROLLER WITH INTER-CORE INTERFERENCE DETECTION  
Embodiments are described for a method for controlling access to memory in a processor-based system comprising monitoring a number of interference events, such as bank contentions, bus...
US20140115276 INTRAPROCEDURAL PRIVATIZATION FOR SHARED ARRAY REFERENCES WITHIN PARTITIONED GLOBAL ADDRESS SPACE (PGAS) LANGUAGES  
Partitioned global address space (PGAS) programming language source code is retrieved by an executed PGAS compiler. At least one shared memory array access indexed by an affine expression that...
US20140108885 HIGH RELIABILITY MEMORY CONTROLLER  
An integrated circuit includes a memory having an address space and a memory controller coupled to the memory for accessing the address space in response to received memory accesses. The memory...
US20140089605 DATA STORAGE DEVICE  
A data storage device may include an interface that is arranged and configured to interface with a host, a command bus, multiple memory devices that are operably coupled to the command bus and a...
US20140089591 SUPPORTING TARGETED STORES IN A SHARED-MEMORY MULTIPROCESSOR SYSTEM  
The present embodiments provide a system for supporting targeted stores in a shared-memory multiprocessor. A targeted store enables a first processor to push a cache line to be stored in a cache...
US20140059286 MEMORY ACCESS DEVICE FOR MEMORY SHARING AMONG PLURALITY OF PROCESSORS, AND ACCESS METHOD FOR SAME  
Provided is a memory access device for a shared memory mechanism of main memory for a plurality of CPUs. The present invention includes a plurality of CPUs using memory as main memory, another...
US20140059283 CONTROLLING A MEMORY ARRAY  
Methods and systems for controlling a memory array are provided. A method of controlling a memory array includes: providing a next index to be read that indicates a location in the memory array...
US20140040566 METHOD AND SYSTEM FOR ACCESSING C++ OBJECTS IN SHARED MEMORY  
The current application discloses methods and systems that access member functions and data fields of C++ objects placed in shared memory as well as cast such objects from multiple processes. The...
US20140040554 Protecting Large Regions without Operating-System Support  
A system and method for providing very large read-sets for hardware transactional memory with limited hardware support by monitoring meta data such as page table entries. The system and method...
US20140040551 REWIND ONLY TRANSACTIONS IN A DATA PROCESSING SYSTEM SUPPORTING TRANSACTIONAL STORAGE ACCESSES  
In a multiprocessor data processing system having a distributed shared memory system, a memory transaction that is a rewind-only transaction (ROT) and that includes one or more transactional...
US20140040532 STACKED MEMORY DEVICE WITH HELPER PROCESSOR  
A processing system comprises one or more processor devices and other system components coupled to a stacked memory device having a set of stacked memory layers and a set of one or more logic...
US20140013060 ENSURING CAUSALITY OF TRANSACTIONAL STORAGE ACCESSES INTERACTING WITH NON-TRANSACTIONAL STORAGE ACCESSES  
A data processing system implements a weak consistency memory model for a distributed shared memory system. The data processing system concurrently executes, on a plurality of processor cores, one...
US20140013055 ENSURING CAUSALITY OF TRANSACTIONAL STORAGE ACCESSES INTERACTING WITH NON-TRANSACTIONAL STORAGE ACCESSES  
A data processing system implements a weak consistency memory model for a distributed shared memory system. The data processing system concurrently executes, on a plurality of processor cores, one...
US20130346700 SYSTEMS AND METHODS FOR MANAGING MEMORY  
A method of accessing data in a shared-memory, parallel-processing computing system, comprises, on a first processing unit, receiving a reference for a data structure stored in a memory and a...
US20130339633 CHANGING A SYSTEM CLOCK RATE SYNCHRONOUSLY  
A system includes a shared memory and a plurality of processor cores communicatively coupled to the shared memory. The system includes a processor core memory and a clock subsystem for providing a...
US20130339631 CROSS-THREADED MEMORY SYSTEM  
In a data processing system, a buffer integrated-circuit (IC) device includes multiple control interfaces, multiple memory interfaces and switching circuitry to couple each of the control...
US20130332679 CIRCUIT FOR MEMORY SHARING  
Disclosed is a memory sharing circuit for sharing a memory, the circuit including a plurality of unit processors connected to the memory, wherein the unit processor includes a buffer configured to...
US20130311726 SHARED MEMORY TRANSLATION FACILITY  
Aspects include a system, method and computer program product for providing a shared memory translation facility. The method includes receiving a request for access to a memory address from a...
US20130290645 TECHNIQUES TO PRELINK SOFTWARE TO IMPROVE MEMORY DE-DUPLICATION IN A VIRTUAL SYSTEM  
Techniques to prelink software to improve memory de-duplication in a virtual system are described. An apparatus may comprise a processor circuit, a memory unit coupled to the processor circuit to...
US20130282989 CONTROL METHOD, MEMORY, AND PROCESSING SYSTEM UTILIZING THE SAME  
A control method for a memory is provided. The memory includes a plurality of storage units, each storing a plurality of bits. In a read mode, a read command is provided to the memory. The value...
US20130262786 MEMORY SYSTEM, METHOD FOR CONTROLLING THE SAME, AND INFORMATION PROCESSING DEVICE  
A memory system method for controlling the same, and an information processing device using the same are provided. The system includes a plurality of memory chips electrically connected with one...
US20130262785 INFORMATION PROCESSING APPARATUS AND SYNCHRONOUS PROCESS EXECUTION MANAGEMENT METHOD  
An information processing apparatus having a storage apparatus shared by a plurality of processors, includes a decision unit that decides, when there is a process to be executed by the plurality...
US20130262783 INFORMATION PROCESSING APPARATUS, ARITHMETIC DEVICE, AND INFORMATION TRANSFERRING METHOD  
An information processing apparatus including a plurarity of nodes. The each of the nodes comprises a processor, a storage device, and a storing unit that stores therein multiple pointer sets in...