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US20100318762 Synchronizing A Translation Lookaside Buffer with Page Tables  
The translation lookaside buffer (TLB) of a processor is kept in synchronization with a guest page table by use of an indicator referred to as a “T” bit. The T bit of the NPT/EPT entries mapping...
US20120159081 DEDUPLICATION-AWARE PAGE CACHE  
An access request that includes a combination of a file identifier and an offset value is received. If the page cache does not contain the page indexed by the combination, then the file system is...
US20150032971 System and Method for Predicting False Sharing  
In one embodiment, a method for predicting false sharing includes running code on a plurality of cores and tracking potential false sharing in the code while running the code to produce tracked...
US20120102272 EFFICIENT FILE MANAGEMENT THROUGH GRANULAR OPPORTUNISTIC LOCKING  
Improved methods and systems for granular opportunistic locking mechanisms (oplocks) are provided for increasing file caching efficiency. Oplocks can be specified with a combination of three...
US20090228646 Maintaining Write Cache and Parity Update Footprint Coherency in Multiple Storage Adaptor Configuration  
A method, computer program product and computer system for maintaining write cache and parity update footprint coherency in a multiple storage adaptor configuration for storage adaptors in a...
US20130159274 User Behavior-Driven Background Cache Refreshing  
Methods and system for providing social feeds from a plurality of third party sites to a user at a host site includes retrieving one or more access logs capturing online behavior of the user. The...
US20150089157 SPECULATIVE READ IN A CACHE COHERENT MICROPROCESSOR  
A cache coherence manager, disposed in a multi-core microprocessor, includes a request unit, an intervention unit, a response unit and an interface unit. The request unit receives coherent...
US20140164714 SPECULATIVE READ IN A CACHE COHERENT MICROPROCESSOR  
A cache coherence manager, disposed in a multi-core microprocessor, includes a request unit, an intervention unit, a response unit and an interface unit. The request unit receives coherent...
US20150089151 SURFACE RESOURCE VIEW HASH FOR COHERENT CACHE OPERATIONS IN TEXTURE PROCESSING HARDWARE  
Techniques are disclosed for performing memory access operations. A texture unit receives a memory access operation that includes a tuple associated with a first view in a plurality of views. The...
US20110264865 TECHNIQUES FOR DIRECTORY SERVER INTEGRATION  
Techniques for directory server integration are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for directory server integration comprising setting...
US20110202793 FAILURE SYSTEM FOR DOMAIN NAME SYSTEM CLIENT  
A method performed by a domain name service client includes storing DNS entries in a local cache; sending a DNS query to another device to obtain an update to one of the DNS entries; determining...
US20120054158 Reduced Disk Space Standby  
A method and system for replicating database data is provided. One or more standby database replicas can be used for servicing read-only queries, and the amount of storage required is scalable in...
US20150089156 Atomic Memory Update Unit & Methods  
In an aspect, an update unit can evaluate condition(s) in an update request and update one or more memory locations based on the condition evaluation. The update unit can operate atomically to...
US20130290642 Managing nodes in a storage system  
Each node in a clustered array is the owner of a set of zero logical disks (LDs). Thinly-provisioned VVs (TPVVs) are partitioned so each is mapped to a group of zero LDs from different sets of...
US20110125971 Shared Upper Level Cache Architecture  
Various implementations of shared upper level cache architectures are disclosed.
US20110208920 FACILITATING SERVER RESPONSE OPTIMIZATION  
A configuration of cached information stored within a cache is determined. One or more character omission rules are determined by: identifying the one or more optimizable characters based on the...
US20140173218 CROSS DEPENDENCY CHECKING LOGIC  
Systems and methods for maintaining an order of transactions in the coherence point. The coherence point stores attributes associated with received transactions in an input request queue (IRQ)....
US20080250210 COPYING DATA FROM A FIRST CLUSTER TO A SECOND CLUSTER TO REASSIGN STORAGE AREAS FROM THE FIRST CLUSTER TO THE SECOND CLUSTER  
Provided are a method, system, and article of manufacture for copying data from a first cluster to a second cluster to reassign storage areas from the first cluster to the second cluster. An...
US20140115269 Multi Domain Bridge with Auto Snoop Response  
An asynchronous dual domain bridge is implemented between the cache coherent master and the coherent system interconnect. The bridge has 2 halves, one in each clock/powerdown domain-master and...
US20110173177 SIGHTFUL CACHE: EFFICIENT INVALIDATION FOR SEARCH ENGINE CACHING  
Updated queries are maintained in a cache. A search engine receives a query from a user through a query entry field. The search engine determines search results corresponding to the user query. A...
US20120324173 EFFICIENT DISCARD SCANS  
Exemplary method, system, and computer program product embodiments for performing a discard scan operation are provided. In one embodiment, by way of example only, a plurality of tracks is...
US20150178205 COHERENCY OVERCOMMIT  
One or more systems, devices, methods, and/or processes described can receive, via an interconnect, messages from processing nodes, and a first portion of the messages can displace a second...
US20140317358 GLOBAL MAINTENANCE COMMAND PROTOCOL IN A CACHE COHERENT SYSTEM  
A system may include a command queue controller coupled to a number of clusters of cores, where each cluster includes a cache shared amongst the cores. An originating core of one of the clusters...
US20140195740 FLOW-ID DEPENDENCY CHECKING LOGIC  
Systems and methods for maintaining an order of transactions in the coherence point. The coherence point stores attributes associated with received transactions in an input request queue (IRQ)....
US20140317359 CLUSTERED FILE SYSTEM CACHING  
A method for accessing data stored in a distributed caching storage system containing a home cluster and a secondary cluster is provided. A first copy of a file is stored on the home cluster and a...
US20150058579 SYSTEMS AND METHODS FOR MEMORY UTILIZATION FOR OBJECT DETECTION  
A method for memory utilization by an electronic device is described. The method includes transferring a first portion of a first decision tree and a second portion of a second decision tree from...
US20140082295 DETECTION OF OUT-OF-BAND ACCESS TO A CACHED FILE SYSTEM  
A network attached storage (NAS) caching appliance, system, and associated method to detect out-of-band accesses to a networked file system.
US20120096228 System and Method for the Synchronization of a File in a Cache  
The present invention provides a system and method for bi-directional synchronization of a cache. One embodiment of the system of this invention includes a software program stored on a computer...
US20130067169 DYNAMIC CACHE QUEUE ALLOCATION BASED ON DESTINATION AVAILABILITY  
An apparatus for controlling operation of a cache includes a first command queue, a second command queue and an input controller configured to receive requests having a first command type and a...
US20110320727 DYNAMIC CACHE QUEUE ALLOCATION BASED ON DESTINATION AVAILABILITY  
An apparatus for controlling operation of a cache includes a first command queue, a second command queue and an input controller configured to receive requests having a first command type and a...
US20110145501 CACHE SPILL MANAGEMENT TECHNIQUES  
An apparatus and method is described herein for intelligently spilling cache lines. Usefulness of cache lines previously spilled from a source cache is learned, such that later evictions of useful...
US20130151788 DYNAMIC PRIORITIZATION OF CACHE ACCESS  
Some embodiments of the inventive subject matter are directed to a cache comprising a tracking unit and cache state machines. In some embodiments, the tracking unit is configured to track an...
US20140115266 OPTIONAL ACKNOWLEDGEMENT FOR OUT-OF-ORDER COHERENCE TRANSACTION COMPLETION  
To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a transaction requires coherent ownership...
US20130282988 Method for Performing Cache Coherency in a Computer System  
In a computing system, cache coherency is performed by selecting one of a plurality of coherency protocols for a first memory transaction. Each of the plurality of coherency protocols has a unique...
US20110016277 Method for Performing Cache Coherency in a Computer System  
In a computing system, cache coherency is performed by selecting one of a plurality of coherency protocols for a first memory transaction. Each of the plurality of coherency protocols has a unique...
US20110320738 Maintaining Cache Coherence In A Multi-Node, Symmetric Multiprocessing Computer  
Maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer composed of a plurality of compute nodes, including, broadcasting upon a cache miss by the first...
US20140181404 INFORMATION COHERENCY MAINTENANCE SYSTEMS AND METHODS  
Systems and methods for coherency maintenance are presented. The systems and methods include utilization of multiple information state tracking approaches or protocols at different memory or...
US20110314228 Maintaining Cache Coherence In A Multi-Node, Symmetric Multiprocessing Computer  
Maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer composed of a plurality of compute nodes, including, broadcasting upon a cache miss by a first compute...
US20110055489 Managing Counter Saturation In A Filter  
Filters and methods for managing presence counter saturation are disclosed. The filters can be coupled to a collection of items and maintain information for determining a potential presence of an...
US20110320739 DISCOVERY OF NETWORK SERVICES  
Discovery of network services consumable by a client executing on a first device. A request is received from the client for a list of services. There is a determination of whether a second device...
US20140122805 SELECTIVE POISONING OF DATA DURING RUNAHEAD  
Embodiments related to selecting a runahead poison policy from a plurality of runahead poison policies during microprocessor operation are provided. The example method includes causing the...
US20080126712 Semiconductor memory system having a snapshot function  
In a semiconductor memory computer equipped with a flash memory, use of backed-up data is enabled. The semiconductor memory computer includes an address conversion table for detecting physical...
US20120089785 APPARATUS AND METHOD FOR DETECTING FALSE SHARING  
A false sharing detecting apparatus for analyzing a multi-thread application, the false sharing detecting apparatus includes an operation set detecting unit configured to detect an operation set...
US20150143050 REUSE OF DIRECTORY ENTRIES FOR HOLDING STATE INFORMATION  
The present application is directed to a control circuit that provides a directory configured to maintain a plurality of entries, wherein each entry can indicate sharing of resources, such as...
US20080313405 Coherency maintaining device and coherency maintaining method  
A second-level cache device stores part of registration information of data for a first-level cache device in a second-level cache-tag unit in association with registration information in a...
US20050262309 Proactive transfer ready resource management in storage area networks  
Systems and methods in accordance with various embodiments can manage transfer ready resources of one or more physical targets to avoid deadlock of a storage switch or storage area network when...
US20140129782 Server Side Distributed Storage Caching  
The invention provides a system with storage cache with high bandwidth and low latency to the server, and coherence for the contents of multiple memory caches, wherein locally managing a storage...
US20140052930 EFFICIENT TRACE CAPTURE BUFFER MANAGEMENT  
A system and method for efficiently storing traces of multiple components in an embedded system. A system-on-a-chip (SOC) includes a trace unit for collecting and storing trace history, bus event...
US20120233410 Shared-Variable-Based (SVB) Synchronization Approach for Multi-Core Simulation  
The present invention discloses a shared-variable-based (SVB) approach for fast and accurate multi-core cache coherence simulation. While the intuitive, conventional approach, synchronizing at...
US20130061003 COHERENCE SWITCH FOR I/O TRAFFIC  
A system, apparatus, and method for routing traffic in a SoC from I/O devices to memory. A coherence switch routes coherent traffic through a coherency port on a processor complex to a real-time...