Match Document Document Title
US20140089572 DISTRIBUTED PAGE-TABLE LOOKUPS IN A SHARED-MEMORY SYSTEM  
The disclosed embodiments provide a system that performs distributed page-table lookups in a shared-memory multiprocessor system with two or more nodes, where each of these nodes includes a...
US20120303884 IMPLEMENTING ENHANCED UPDATES FOR INDIRECTION TABLES  
A method and a storage system are provided for implementing indirection tables and providing enhanced updates of the indirection tables for persistent media or disk drives, such as shingled...
US20120137060 Multi-stage TCAM search  
A method to divide a database of TCAM rules includes selecting a rule of the database having multiple don't care values and selecting a bit of the rule having a don't care value, generating two...
US20110161639 Event counter checkpointing and restoring  
A method of one aspect may include storing an event count of an event counter that counts events that occur during execution within a logic device. The method may further include restoring the...
US20130339592 APPROACH TO VIRTUAL BANK MANAGEMENT IN DRAM CONTROLLERS  
Banks within a dynamic random access memory (DRAM) are managed with virtual bank managers. A DRAM controller receives a new memory access request to DRAM including a plurality of banks. If the...
US20110153307 Transitioning From Source Instruction Set Architecture (ISA) Code To Translated Code In A Partial Emulation Environment  
In one embodiment, a processor can operate in multiple modes, including a direct execution mode and an emulation execution mode. More specifically, the processor may operate in a partial emulation...
US20130304968 DEMOTING TRACKS FROM A FIRST CACHE TO A SECOND CACHE BY USING AN OCCUPANCY OF VALID TRACKS IN STRIDES IN THE SECOND CACHE TO CONSOLIDATE STRIDES IN THE SECOND CACHE  
Information is maintained on strides configured in a second cache and occupancy counts for the strides indicating an extent to which the strides are populated with valid tracks and invalid tracks....
US20110066796 AUTONOMOUS SUBSYSTEM ARCHITECTURE  
An autonomous sub-system receives a database downloaded from a host controller. A controller monitors bus traffic and/or allocated resources in the subsystem and re-allocates resources based on...
US20140310552 REDUCED-POWER SLEEP STATE S3  
Current computer systems support sleep states such as sleep state S3 and sleep state S4. A system in sleep state S3 utilizes more power than one in sleep state S4, however, a system in sleep state...
US20140372691 COUNTER POLICY IMPLEMENTATION  
According to an example, a counter policy implementation apparatus may include a policy determination module to receive a counter address for a local counter and to map the counter address to a...
US20100082881 SOLID STATE STORAGE DEVICE CONTROLLER WITH EXPANSION MODE  
Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the...
US20150067248 DRAM CONTROLLER HAVING DRAM BAD PAGE MANAGEMENT FUNCTION AND BAD PAGE MANAGEMENT METHOD THEREOF  
A bad page management system is provided to guarantee a yield of a volatile semiconductor memory device such as a DRAM. A bad page list exists in a DRAM. A page remapper in a memory controller...
US20050108460 Partial bank DRAM refresh  
A “partial refresh command” is used to refresh a fraction of the banks in a multi-bank DRAM. In a first implementation the command refreshes one half of the banks. In a second implementation the...
US20100122020 DYNAMIC PERFORMANCE VIRTUALIZATION FOR DISK ACCESS  
A storage control system includes performance monitor logic configured to track performance parameters for different volumes in a storage array. Service level enforcement logic is configured to...
US20120173811 Method and Apparatus for Delaying Write Operations  
An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit to the DRAM a first code to indicate that first data is to be written to the...
US20110066788 CONTAINER MARKER SCHEME FOR REDUCING WRITE AMPLIFICATION IN SOLID STATE DEVICES  
A solid state storage device and method are provided. Multiple blocks are configured as storage memory for a solid state storage device, and each block includes multiple pages. A controller is...
US20130185495 DEMOTING TRACKS FROM A FIRST CACHE TO A SECOND CACHE BY USING A STRIDE NUMBER ORDERING OF STRIDES IN THE SECOND CACHE TO CONSOLIDATE STRIDES IN THE SECOND CACHE  
Information on strides configured in the second cache includes information indicating a number of valid tracks in the strides, wherein a stride has at least one of valid tracks and free tracks not...
US20120072652 MULTI-LEVEL BUFFER POOL EXTENSIONS  
A buffer manager that manages blocks of memory amongst multiple levels of buffer pools. For instance, there may be a first level buffer pool for blocks in first level memory, and a second level...
US20130166834 SUB PAGE AND PAGE MEMORY MANAGEMENT APPARATUS AND METHOD  
A method and apparatus for managing a virtual address to physical address translation utilize a subpage level fault detecting and access. The method and apparatus may also use an additional...
US20110314210 LEVERAGING CHIP VARIABILITY  
Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring...
US20120079180 DRAM Controller and a method for command controlling  
A memory controller and a command control method are disclosed. When there is a need to access an unactivated bank in an external DRAM, an ACT command and an access command of a low rate are...
US20100005234 Enabling functional dependency in a multi-function device  
In one embodiment, the present invention includes a method for reading configuration information from a multi-function device (MFD), building a dependency tree of a functional dependency of...
US20080195887 DRAM CACHE WITH ON-DEMAND RELOAD  
Embodiments include a DRAM cache structure, associated circuits and method of operations suitable for use with high-speed caches. The DRAM caches do not require regular refresh of its data and...
US20130185494 POPULATING A FIRST STRIDE OF TRACKS FROM A FIRST CACHE TO WRITE TO A SECOND STRIDE IN A SECOND CACHE  
Provided are a computer program product, system, and method for managing data in a cache system comprising a first cache, a second cache, and a storage system. A determination is made of tracks...
US20130185478 POPULATING A FIRST STRIDE OF TRACKS FROM A FIRST CACHE TO WRITE TO A SECOND STRIDE IN A SECOND CACHE  
Provided are a computer program product, system, and method for managing data in a cache system comprising a first cache, a second cache, and a storage system. A determination is made of tracks...
US20090327774 COORDINATED LINK POWER MANAGEMENT  
A method, apparatus, and system for coordinated link power management. Some embodiments of a method include receiving an exit latency for each of a group of link states for a link, with a device...
US20120226852 CONTROL METHOD AND CONTROLLER FOR DRAM  
A DRAM controller including a judging module, a determination module, and a transmission module is provided. The judging module judges an address content difference between a first command and a...
US20110320694 CACHED LATENCY REDUCTION UTILIZING EARLY ACCESS TO A SHARED PIPELINE  
A method of performing operations in a shared cache coupled to a first requestor and a second requestor includes receiving at the shared cache a first request from the second requester; assigning...
US20090172316 MULTI-LEVEL PAGE-WALK APPARATUS FOR OUT-OF-ORDER MEMORY CONTROLLERS SUPPORTING VIRTUALIZATION TECHNOLOGY  
The invention relates generally to computer memory access. Embodiments of the invention provide a multi-level page-walk apparatus and method that enable I/O devices to execute multi-level...
US20140181385 FLEXIBLE UTILIZATION OF BLOCK STORAGE IN A COMPUTING SYSTEM  
Embodiments of the present invention disclose a method, computer program product, and system for utilizing a block storage device as Dynamic Random-Access Memory (DRAM) space, wherein a computer...
US20140032829 Energy Conservation in a Multicore Chip  
Technologies are described herein for conserving energy in a multicore chip via selectively refreshing memory directory entries. Some described examples may refresh a dynamic random access memory...
US20140325136 CONFIGURATION FOR POWER REDUCTION IN DRAM  
Disclosed embodiments may include an apparatus having a segment wordline enable coupled to logic to selectively disable ones of a number of segment wordline drivers. The logic may partition a page...
US20140006700 CONFIGURATION FOR POWER REDUCTION IN DRAM  
Disclosed embodiments may include an apparatus having a segment wordline enable coupled to logic to selectively disable ones of a number of segment wordline drivers. The logic may partition a page...
US20080120457 Apparatuses for synchronous transfer of information  
Semiconductor devices provide for synchronous transfer of information through a data bus. Address, control and clock information is received, via a command bus and clock line, at a plurality of...
US20090031078 Rank sparing system and method  
A system, and a corresponding method, are used to implement rank sparing. The system includes a memory controller and one or more DIMM channels coupled to the memory controller, where each DIMM...
US20140351501 MESSAGE STORAGE IN MEMORY BLOCKS USING CODEWORDS  
A codeword is generated from a message. One or more anchor values are appended to the codeword at predetermined anchor positions. Before the codeword is stored in a memory block, the locations and...
US20070028026 Digital multimedia transfer rate controlling  
An apparatus that includes a controller to regulate a rate of transfer of MPEG transport stream packets from a first storage device to a second storage device based on transfer rate control...
US20120233393 Scheduling Workloads Based On Cache Asymmetry  
In one embodiment, a processor includes a first cache and a second cache, a first core associated with the first cache and a second core associated with the second cache. The caches are of...
US20140325135 TERMINATION IMPEDANCE APPARATUS WITH CALIBRATION CIRCUIT AND METHOD THEREFOR  
A termination impedance apparatus includes a variable pull-up resistor, a variable pull-down resistor, and a small-signal calibration circuit. The variable pull-up resistor is coupled between a...
US20050240717 Interleaved Mapping Method of Block-Index-To-SDRAM-Address for Optical Storage (CD/DVD) System  
A method for storing data into a SRDAM. The method comprises the following steps: receiving a plurality of blocks of data; labeling said blocks successively from 1 in step of 1; dividing the label...
US20090282194 Removable storage accelerator device  
An accelerator device including a cache memory, a controller that is electrically coupled to the cache memory, a host computer connecter that is electrically coupled to the controller, and a...
US20100020584 High Speed Memory Module  
A memory module may include a circuit board connectable to a system memory bus through a plurality of contacts disposed along one edge of the circuit board, the system memory bus having three...
US20090319708 ELECTRONIC SYSTEM AND RELATED METHOD WITH TIME-SHARING BUS  
An electronic system with time-sharing bus includes a controller, a storage element, a first electronic element, and a shared bus. The controller receives a command to generate a set of enable...
US20130185497 MANAGING CACHING OF EXTENTS OF TRACKS IN A FIRST CACHE, SECOND CACHE AND STORAGE  
Provided are a computer program product, system, and method for managing caching of extents of tracks in a first cache, second cache and storage device. A determination is made of an eligible...
US20130185493 MANAGING CACHING OF EXTENTS OF TRACKS IN A FIRST CACHE, SECOND CACHE AND STORAGE  
Provided are a computer program product, system, and method for managing caching of extents of tracks in a first cache, second cache and storage device. A determination is made of an eligible...
US20110161783 METHOD AND APPARATUS ON DIRECT MATCHING OF CACHE TAGS CODED WITH ERROR CORRECTING CODES (ECC)  
An apparatus and method is described herein directly matching coded tags. An incoming tag address is encoded with error correction codes (ECCs) to obtain a coded, incoming tag. The coded, incoming...
US20140047175 IMPLEMENTING EFFICIENT CACHE TAG LOOKUP IN VERY LARGE CACHE SYSTEMS  
A method and circuit for implementing a cache directory and efficient cache tag lookup in very large cache systems, and a design structure on which the subject circuit resides are provided. A tag...
US20110320702 Operation Frequency Adjusting System and Method  
Techniques pertaining to adjusting the operation frequency of a DRAM are disclosed. According to one embodiment, the DRAM operation frequency adjusting system includes a statistic module counting...
US20130103898 DRIVER FOR DDR2/3 MEMORY INTERFACES  
An apparatus is described that includes a combined drive and termination circuit programmable to interface to DDR2 and DDR3 memory modules. In an exemplary embodiment the apparatus includes a...
US20080005455 Fast transition from low-speed mode to high-speed mode in high-speed interfaces  
Embodiments directed to a memory device and a memory controller that continue to operate in a low-power mode during the period required for analog timing circuitry to initialize and become usable,...