Matches 1 - 50 out of 112 1 2 3 >


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US20110138099 Method for communicating between nodes and server apparatus  
According to an aspect of the embodiment, an input/output device transmits a message to a first node controller of a parent node which is set in advance via a cross bar. At this point, the cross...
US20110060860 BACKPLANE NETWORK DISTRIBUTION  
A backplane arrangement 200; 500 and method for distributing network connections in said backplane arrangement 200; 500 comprising a number of board positions Ac-Fc; Gc-Kc each arranged to...
US20140281112 METHOD AND APPARATUS FOR DYNAMIC POWER SAVING WITH FLEXIBLE GATING IN A CROSS-BAR ARCHITECTURE  
Various aspects of dynamic power reduction in a bus communication architecture are described herein as embodied in an XBAR architecture that provides flexible gating of multiple paths and repeater...
US20140025862 SERVER SYSTEM AND DYNAMIC MAINTENANCE METHOD FOR CROSSBAR BOARD  
According to an aspect of an embodiment, a server system includes a service processor, a plurality of system boards and a plurality of crossbar boards connecting the system boards. The service...
US20070276982 THIRD SWITCH FOR VXS/VMEBUS COMPLIANT COMPUTING SYSTEM  
Embodiments of the present invention take advantage of the extra slot and connectors in the P0/J0 position that are reserved for future use in the VXS standard to create a VXS-compliant backplane...
US20110173358 EAGER PROTOCOL ON A CACHE PIPELINE DATAFLOW  
A master device sends a request to communicate with a slave device to a switch. The master device waits for a period of cycles the switch takes to decide whether the master device can communicate...
US20140289445 HARDWARE ACCELERATOR SYSTEM AND METHOD  
There is provided a hardware accelerator system and method. The system and method relate to a low power scalable stream compute accelerator for general matrix multiply (GEMM). There is provided a...
US20070124529 Subrack with front and rear insertion of AMC modules  
A subrack having a front side and a rear side, wherein the subrack is coupled to receive an Advanced Mezzanine Card module, the subrack includes a backplane having a first side and second side,...
US20100077127 Flexible Connection Scheme Between Multiple Masters and Slaves  
The present invention describes a flexible routing scheme between masters and slaves in complex digital systems. The routing scheme is optimized for maximum versatility and configurability using...
US20130046915 Scalable and Configurable System on a Chip Interrupt Controller  
Embodiments include a system and method for an interrupt controller that propagates interrupts to a subsystem in a system-on-a-chip (SOC). Interrupts are provided to an interrupt controller that...
US20140040528 RECONFIGURABLE CROSSBAR NETWORKS  
Reconfigurable crossbar networks, and devices, systems and methods, including hardware in the form of logic (e.g. application specific integrated circuits (ASICS)), and software in the form of...
US20060212642 Partition allocation method and computer system  
In a computer system in which a plurality of processor boards and a plurality of input and output (I/O) boards are coupled via an address and data crossbar, a partition allocation method allocates...
US20090198864 NETWORK SWITCH AND METHOD OF SWITCHING IN NETWORK  
A network switch with a plurality of crossbar switches that is available to suppress increase in the circuit scale is provided. The network switch has: the plurality of crossbar switches that...
US20100211718 METHOD AND APPARATUS FOR CONGESTION-AWARE ROUTING IN A COMPUTER INTERCONNECTION NETWORK  
The present disclosure relates to an example of a method for a first router to adaptively determine status within a network. The network may include the first router, a second router and a third...
US20140032811 MULTI-ROOT PERIPHERAL CONNECT INTERFACE MANAGER  
Described herein is a detachable multi-host computing system (100) having multiple host processors running different operating systems. In one implementation, the multi-host computing system (100)...
US20140075085 METHOD AND APPARATUS FOR TRANSFERRING PACKETS BETWEEN INTERFACE CONTROL MODULES OF LINE CARDS  
An access system includes line cards. The line cards include first and second line cards. The first line card receives a first packet and includes a first interface control module that generates a...
US20150019790 COMMUNICATIONS CONTROL SYSTEM WITH A SERIAL COMMUNICATIONS INTERFACE AND A PARALLEL COMMUNICATIONS INTERFACE  
A communications control system is disclosed that includes a serial communications interface and a parallel communications interface for coupling a plurality of input/output modules with a control...
US20130173840 COMMUNICATIONS CONTROL SYSTEM WITH A SERIAL COMMUNICATIONS INTERFACE AND A PARALLEL COMMUNICATIONS INTERFACE  
A communications control system is disclosed that includes a serial communications interface and a parallel communications interface for coupling a plurality of input/output modules with a control...
US20110258361 PETAFLOPS ROUTER  
Disclosed is a method and system for performing operations on at least one input data vector in order to produce at least one output vector to permit easy, scalable and fast programming of a...
US20140281113 HOST INTERFACE CROSSBAR FOR SENSOR HUB  
A microcontroller for a peripheral hub includes a plurality of host bus interface microdrivers and a corresponding plurality of host transports. A first manager client, associated with a supported...
US20140189190 MECHANISM FOR FACILITATING DYNAMIC CANCELLATION OF SIGNAL CROSSTALK IN DIFFERENTIAL INPUT/OUTPUT CHANNELS  
A mechanism is described for facilitating dynamic cancellation of signal crosstalk in input/output differential channels according to one embodiment. A method of embodiments may include detecting...
US20080046629 DATA PROCESSING MANAGEMENT APPARATUS, MODE MANAGEMENT APPARATUS AND MODE MANAGEMENT METHOD  
A configuration is such as to change a mode setup of other crossbars influenced by an error occurring in one of plural crossbars from a first mode to a second mode for operating each of them...
US20110035529 Partitioning a Crossbar Interconnect in a Multi-Channel Memory System  
A method includes identifying a first set of masters and a second set of masters from a plurality of masters. The plurality of masters have access to a multi-channel memory via a crossbar...
US20080147954 Crossbar arithmetic and summation processor  
A processor includes a crossbar array including row wires and column wires wherein bit patterns representative of numerical values are stored in a plurality of columns of the crossbar array in the...
US20050117575 Nonblocking and deterministic unicast packet scheduling  
A system for scheduling unicast packets through an interconnection network having a plurality of input ports, a plurality of output ports, and a plurality of input queues, comprising unicast...
US20090307408 Peer-to-Peer Embedded System Communication Method and Apparatus  
According to one embodiment, an embedded system includes at least one processor, memory and peripheral subsystem. Each subsystem has a terminating node configured to issue and receive messages for...
US20100138586 ADAPTIVE AND MODULAR UPS SYSTEM AND METHOD  
An uninterruptible power supply (UPS) system that may incorporate a battery subsystem including at least one battery for generating electrical power, and a UPS subsystem including at least one...
US20130046916 FIBRE ADAPTER FOR A SMALL FORM-FACTOR PLUGGABLE UNIT  
The disclosure is directed at a fibre adapter for use with small form factor pluggable (SFP) devices comprising a set of cages for receiving the SFP devices and a switch for interconnecting inputs...
US20060206657 Single port/multiple ring implementation of a hybrid crossbar partially non-blocking data switch  
A ring-based crossbar data switch, a method and a computer program are provided for the transfer of data between multiple bus units in a memory system. Each bus unit is connected to a...
US20120324140 CODING FOR CROSSBAR ARCHITECTURE  
A method for encoding bits to be stored within a crossbar memory architecture performed by a physical computing system includes designating, with the physical computing system, a subset of...
US20080307151 Operational amplifier with resistance switch crossbar feedback  
A control circuit includes an operational amplifier having an inverting input, a non-inverting input, and an output, an array of impedance elements including capacitors are connected to the output...
US20060161718 System and method for a non-uniform crossbar switch plane topology  
A system and method for communicatively coupling a plurality of processor groups residing in a symmetric multiprocessing (SMP) system. One embodiment of a non-uniform crossbar switch plane...
US20090177870 Method and System for a Wiring-Efficient Permute Unit  
A method of providing wiring efficiency in a permute unit. Multiple selectors receive input data and shared control signals from multiple register files. The permute unit includes multiple...
US20080155138 DATAPIPE CPU REGISTER ARRAY  
A system for data processing comprises a host circuit (104) and an integrated circuit (102), the host circuit (104) being external to the integrated circuit (102). The integrated circuit (102)...
US20090240866 Multi-port memory and computer system provided with the same  
A multi-port memory, comprising: m (m≧2) input/output ports independent of one another; n (n≧2) memory banks independent of one another; and a route switching circuit capable of optionally setting...
US20080059687 SYSTEM AND METHOD OF CONNECTING A PROCESSING UNIT WITH A MEMORY UNIT  
A method and system comprising at least two processing units that are connected with at least two memory units, wherein first data buses are connected with the memory units, wherein second data...
US20080106951 Architecture for an output buffered switch with input groups  
Embodiments of the present invention provide a system that transfers data between the components in the computer system through a switch. In these embodiments, the switch includes multiple switch...
US20120159037 MEMORY INTERLEAVING DEVICE AND METHOD USING REORDER BUFFER  
A memory interleaving device includes a slave interface, a master interface, and a crossbar switch. The slave interface is connected with a master intellectual property through an on-chip network....
US20090210610 Computer system, data relay device and control method for computer system  
A computer system includes a plurality of system boards each of which includes two systems arranged in a duplicated structure and a data relay device. The data relay device includes a degeneration...
US20140344501 NETWORK-ON-CHIP ARCHITECTURE FOR MULTI-PROCESSOR SOC DESIGNS  
A system and method embodying some aspects for communicating between nodes in a network-on-chip are provided. The system comprises a microprocessing chip and a plurality of connection paths. The...
US20140122771 WEIGHTAGE-BASED SCHEDULING FOR HIERARCHICAL SWITCHING FABRICS  
Techniques are disclosed to implement a scheduling scheme for a crossbar scheduler that provides distributed request-grant-accept arbitration between input group arbiters and output group arbiters...
US20100005213 Access Table Lookup for Bus Bridge  
Cross-bar segment routing and access table address remapping functions are combined within a cross-bar of a system-on-a-chip. In this manner, address remapping may occur prior to segment routing....
US20150154136 INPUT/OUTPUT MODULE WITH MULTI-CHANNEL SWITCHING CAPABILITY  
The present disclosure is directed to an input/output module. In some embodiments, the input/output module includes: a plurality of communication channels, each channel of the plurality of...
US20080126620 Coupling data buffers with memory interfaces  
In one embodiment, the present invention includes a method including receiving a read request at a first buffer from a first one of multiple interfaces and forwarding the read request from the...
US20090172242 SYSTEM AND METHOD FOR CONNECTING A MASTER DEVICE WITH MULTIPLE GROUPINGS OF SLAVE DEVICES VIA A LINBUS NETWORK  
A LINBUS communication network comprises a microcontroller unit containing processing circuitry for performing predefined digital processing functions. LINBUS communication network hardware is...
US20150212955 Programmable Interrupt Routing in Multiprocessor Devices  
A multiprocessor device is provided that includes a plurality of processors in which each processor of the plurality of processors includes an interrupt controller, and a symmetric interrupt...
US20110055452 METHOD AND PROGRAM FOR MEMORY RELOCATION CONTROL OF COMPUTER, AND COMPUTER SYSTEM  
A computer system comprises a computer that includes a plurality of CPU sockets including one or more CPU cores, a crossbar switch, and a memory controller each, and memories connected under the...
US20070186027 Method and apparatus for implementing control of a multiple ring hybrid crossbar partially non-blocking data switch  
A method and control apparatus are provided for implementing control of a multiple-ring hybrid crossbar partially non-blocking data switch, the data switch including a plurality of bus units, each...
US20090249127 METHOD AND SYSTEM FOR STORING DATA FROM A PLURALITY OF PROCESSORS  
A method of storing data from a plurality of processors comprising the steps of (a) transferring data along a first bus (b) connectable between a first processor and a synchronising means and...
US20050125590 PCI express switch  
A PCI Express switch utilizes a central crossbar memory for all ports of the switch. The crossbar memory retains the packet that is to be sent out and only the head pointer for the packet is...

Matches 1 - 50 out of 112 1 2 3 >