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US20110302343 SYSTEMS AND METHODS FOR PROVIDING INSTANT-ON FUNCTIONALITY ON AN EMBEDDED CONTROLLER  
Systems and methods for providing instant-on functionality on an embedded controller are disclosed. A method of providing instant-on functionality on a controller comprises an initial state, an...
US20110099357 Utilizing a Bidding Model in a Microparallel Processor Architecture to Allocate Additional Registers and Execution Units for Short to Intermediate Stretches of Code Identified as Opportunities for Microparallelization  
An enhanced mechanism for parallel execution of computer programs utilizes a bidding model to allocate additional registers and execution units for stretches of code identified as opportunities...
US20120131249 METHODS AND SYSTEMS FOR AN INTERPOSER BOARD  
In accordance with at least some embodiments, a system (100) includes an aggregator backplane (124) coupled to a plurality of fans (120A-120N) and power supplies (122A-122N) and configured to...
US20080065804 Event handling for architectural events at high privilege levels  
Methods and apparatus to perform event handling operations are described. In one embodiment, after an event (such as an architectural event occurs), the corresponding occurrence response (e.g., a...
US20120254492 TRAFFIC CLASS BASED ADAPTIVE INTERRUPT MODERATION  
An apparatus which comprises two or more moderation timers associated with an interrupt vector is presented. In one embodiment, the apparatus comprises two or more interrupt vectors and moderation...
US20110107426 COMPUTING SYSTEM USING SINGLE OPERATING SYSTEM TO PROVIDE NORMAL SECURITY SERVICES AND HIGH SECURITY SERVICES, AND METHODS THEREOF  
A method of providing normal security services and high security services with a single operating system in a computing system is disclosed. A secure thread is only accessible while the computing...
US20150067220 REAL-TIME EMBEDDED SYSTEM  
A real-time operating system (OS) for an embedded system may be configured for asynchronous handling of input and output (I/O) operations. When application code is executing, the OS may be...
US20110320664 CONTROLLING A RATE AT WHICH ADAPTER INTERRUPTION REQUESTS ARE PROCESSED  
The conditions under which adapter interruptions are made pending are controlled. Responsive to an interruption being presented to an operating system, subsequent interruptions are suppressed on...
US20110246696 Interrupt Vector Piggybacking  
A hypervisor receives an interrupt that includes a target address and, in turn, branches to an administrating interrupt vector. Next, the administrating interrupt vector determines whether to...
US20060265536 User-defined interrupt signal handling method and system  
A user-defined interrupt signal handling method and system is proposed, which is designed for use with a computer platform equipped with a programmable interrupt controller for providing a...
US20060294277 Message signaled interrupt redirection  
A method, device, and system are disclosed. In one embodiment, the method comprises receiving a message signaled interrupt, parsing an interrupt vector from the message signaled interrupt,...
US20150193616 MITIGATING JUST-IN-TIME SPRAYING ATTACKS IN A NETWORK ENVIRONMENT  
An example method for mitigating JIT spraying attacks in a network environment is provided and includes protecting an output of a just-in-time (JIT) compiler against attacks during application...
US20080162761 INTERRUPT CONTROL CIRCUIT, CIRCUIT BOARD, ELECTRO-OPTIC DEVICE, AND ELECTRONIC APPARATUS  
An interrupt control circuit includes: a section that generates an interrupt signal for requesting an interrupt in response to occurrence of a plurality of interrupt causes; a section that...
US20110153894 INTERRUPT-HANDLING-MODE DETERMINING METHOD OF EMBEDDED OPERATING SYSTEM KERNEL  
Provided is a method capable of providing an improved response property appropriate for the characteristics of a system by automatically choosing an interrupt handling mode used for each device....
US20110066783 Secure Handling and Routing of Message-Signaled Interrupts  
Encryption of interrupt vectors and authentication of device drivers prevents unauthorized modules from interfering with an interrupt handler. An operating system may encrypt an interrupt vector...
US20140195709 DELIVERING REAL TIME INTERRUPTS WITH AN ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER  
Embodiments of apparatuses and methods for delivering real time interrupts with an APIC are disclosed. In one embodiment, an apparatus includes a local advanced programmable interrupt controller...
US20100005264 INFORMATION PROCESSING DEVICE, INTEGRATED CIRCUIT, METHOD, AND PROGRAM  
To aim to provide an information processing device capable of improving a processing capability and securely handling programs and data to be protected. According to a system LSI 100 including a...
US20140059262 TASK SCHEDULING IN BIG AND LITTLE CORES  
One aspect provides a method comprising: ascertaining an interrupt at an information handling device having two or more cores of different size; determining if the interrupt should be directed to...
US20080098146 Interrupt hooking method for a computing apparatus  
An interrupt hooking method for a computing apparatus, which includes a processing device and an interrupt controller, includes the steps of: enabling the processing device to convert a hardware...
US20130103872 COMPUTER APPARATUS AND METHOD FOR DISTRIBUTING INTERRUPT TASKS THEREOF  
A computer apparatus and a method for distributing interrupt tasks thereof are provided. The computer apparatus has a plurality of CPUs and a chipset, and the chipset is electrically coupled to...
US20150186306 METHOD AND AN APPARATUS FOR CONVERTING INTERRUPTS INTO SCHEDULED EVENTS  
A method and an apparatus embodying the method for converting interrupts into scheduled events, comprising receiving an interrupt at an interrupt controller; determining a vector number for the...
US20110320665 Managing Concurrent Serialized Interrupt Broadcast Commands In A Multi-Node, Symmetric Multiprocessing Computer  
Managing concurrent serialized interrupt broadcast commands in a multi-node, symmetric multiprocessing computer including receiving, by a communications adapter in a compute node, a plurality of...
US20130054858 METHOD AND SYSTEM FOR CONDITIONAL INTERRUPTS  
A method for issuing interrupts includes a receiving communication adapter receiving a first remote directed memory access (RDMA) write with immediate, identifying a completion queue descriptor...
US20080016264 METHOD AND SYSTEM FOR HANDLING USER-DEFINED INTERRUPT REQUEST  
A method and a system for handling a user-defined interrupt request (IRQ) are provided. In the present invention, an interrupt configuration table which records the correspondence between a device...
US20140351472 METHOD AND APPARATUS FOR INTERRUPT HANDLING  
A data processing device comprises a plurality of system registers and a set of interrupt handling registers for controlling handling of an incoming interrupt. The device also includes processing...
US20120198114 CONVERTING A MESSAGE SIGNALED INTERRUPTION INTO AN I/O ADAPTER EVENT NOTIFICATION TO A GUEST OPERATING SYSTEM  
One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications while retaining the message vector indication. An...
US20110320663 CONVERTING A MESSAGE SIGNALED INTERRUPTION INTO AN I/O ADAPTER EVENT NOTIFICATION TO A GUEST OPERATING SYSTEM  
One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications while retaining the message vector indication. An...
US20110191513 INTERRUPT CONTROL METHOD AND SYSTEM  
An interrupt control system comprises: a central processing unit (CPU); a peripheral device; an interrupt controller, and an interrupt preprocessing circuit. The peripheral device optionally...
US20110321061 CONVERTING A MESSAGE SIGNALED INTERRUPTION INTO AN I/O ADAPTER EVENT NOTIFICATION  
One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications. Each I/O adapter event notification includes the...
US20120179851 Computer System Interrupt Handling  
A system, method and article of manufacture for an accelerated processing device (APD) to request a central processing unit (CPU) to process a task, comprising enqueuing a plurality of tasks on a...
US20100023667 HIGH AVAILABILITY SYSTEM AND EXECUTION STATE CONTROL METHOD  
A high availability system includes a first server computer for a first virtual computer and a first hypervisor and a second server computer for a second virtual computer and a second hypervisor....
US20100036987 Apparatus and Methods for Speculative Interrupt Vector Prefetching  
Techniques for interrupt processing are described. An exceptional condition is detected in one or more stages of an instruction pipeline in a processor. In response to the detected exceptional...
US20140229648 Storing Interrupt Location for Fast Interrupt Register Access In Hypervisors  
Methods, systems, and computer program products for using a stored interrupt location to provide fast interrupt register access in hypervisors are presented. A computer-implemented method may...
US20140344492 METHODS AND SYSTEMS FOR REDUCING SPURIOUS INTERRUPTS IN A DATA STORAGE SYSTEM  
A storage controller of a data storage system maintains, for each interrupt vector, (1) a pending status that indicates whether one or more completions are pending in the completion queue (CQ)...
US20120226845 Hardware interrupt processing circuit  
A hardware interrupt processing circuit converts selected hardware interrupts to an interrupt vector having bits corresponding to the selected hardware interrupts. The hardware interrupt...
US20140136746 TECHNIQUE FOR COMMUNICATING INTERRUPTS IN A COMPUTER SYSTEM  
A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of bits within an...
US20100191888 Guest Interrupt Manager to Aid Interrupt Virtualization  
In an embodiment, a system comprises a memory system and a guest interrupt manager. The guest interrupt manager is configured to receive an interrupt message corresponding to an interrupt that is...
US20120203947 ON-DEMAND INTERRUPT VECTOR ALLOCATION BASED ON ACTIVITY DETECTION  
A method and system for dynamically allocating interrupt vectors on demand. A computer system measures a rate of activities associated with an event. Based on the rate of activities, the computer...
US20090172233 METHODS AND APPARATUS FOR HALTING CORES IN RESPONSE TO SYSTEM MANAGEMENT INTERRUPTS  
A method includes halting at least one processing core of a computer system in response to a system management interrupt. The method further includes handling the system management interrupt with...
US20110145462 Implementing Gang Interrupts  
A method includes receiving a first interrupt request from a first device instance of a plurality of device instances. The first interrupt request is requesting an interrupt of a processor. The...
US20150074311 SIGNAL INTERRUPTS IN A TRANSACTIONAL MEMORY SYSTEM  
In some embodiments, a method includes executing an atomic transaction in a system having a transactional memory. The method includes receiving a signal interrupt during executing of the atomic...
US20130275639 METHOD TO EMULATE MESSAGE SIGNALED INTERRUPTS WITH MULTIPLE INTERRUPT VECTORS  
Methods to emulate a message signaled interrupt (MSI) with multiple interrupt vectors are described herein. An embodiment of the invention includes a memory decoder to monitor a predetermined...
US20120137053 MICROPROCESSOR  
A microprocessor to be connected with an external device is disclosed. The microprocessor includes a non-rewritable memory including a first interrupt vector table storing addresses of plural...
US20130290587 MICROCOMPUTER  
A rewriting area of a flash ROM stores a main program, which includes a user vector with respect to each of interrupt factors that are different from each other in respect of types. The user...
US20090204740 Method and Device for Performing Switchover Operations in a Computer System Having at Least Two Execution Units  
A method and device for performing switchover operations in a computer system having at least two execution units are provided, in which switchover units are included which are configured in such...
US20150143016 METHOD AND APPARATUS FOR DELIVERING MSI-X INTERRUPTS THROUGH NON-TRANSPARENT BRIDGES TO COMPUTING RESOURCES IN PCI-EXPRESS CLUSTERS  
An apparatus for initialization. The apparatus includes a management I/O device controller for managing initialization of a plurality of I/O devices coupled to a PCI-Express (PCIe) fabric. The...
US20140207989 ACCESS CONTROL TO A JOINTLY EXCLUSIVELY USABLE TRANSMISSION MEDIUM  
A computing system and a method are specified. The computing system has a plurality of components which are configured to use a resource exclusively jointly, an activity monitoring unit which...
US20110138082 Host-Based Messaging Framework for PCIe Device Management  
A method of routing data in an information handling system can include receiving a notification from a management controller at a basic input/output system (BIOS) that includes a system management...
US20100191889 MEMORY STRUCTURE TO STORE INTERRUPT STATE FOR INACTIVE GUESTS  
In an embodiment, a system comprises a memory system configured to store a data structure. The data structure stores at least an interrupt request state for each destination in each of a plurality...
US20120036292 POLLING IN A VIRTUALIZED INFORMATION HANDLING SYSTEM  
A software thread is dispatched for causing the system to poll a device for determining whether a condition has occurred. Subsequently, the software thread is undispatched and, in response...

Matches 1 - 50 out of 99 1 2 >