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US20150186308 |
METHOD AND AN APPARATUS FOR INTERUPT COLLECTING AND REPORTING
A method and a system embodying the method for interrupt collecting an reporting, comprising: storing for each of at least one interrupt a status indicator, an enable status, and an interrupt... |
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US20150234757 |
SECURITY INFORMATION INPUTTING/OUTPUTTING METHOD AND ELECTRONIC DEVICE ADAPTED TO THE METHOD
A method is provided that inputs/outputs security information to/from an electronic device. The security information inputting method includes sensing a motion for inputting security information... |
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US20140250251 |
AUTOMATICALLY AND TRANSPARENTLY PRESERVING TESTING STATE ACROSS SESSIONS
Disclosed is a technique for an automated testing harness that transparently preserves testing state across system sessions. The testing harness can be configured to execute a script of testing... |
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US20110202699 |
PREFERRED INTERRUPT BINDING
A method and system for binding interrupts to central processing units (CPUs). An interrupt controller receives an interrupt that is generated by a device coupled to the computer system. The... |
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US20150149676 |
SYSTEM FOR FORMULATING TEMPORAL BASES FOR OPERATION OF PROCESSES FOR PROCESS COORDINATION
A novel approach to coordinate processes in a process environment includes establishing a coherent temporal and resource framework for operation of selected processes in order to formulate a basis... |
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US20150113191 |
RESOURCE SERIALIZATION IN A TRANSACTIONAL EXECUTION FACILITY
Embodiments include methods, systems and computer program products that include executing a begin transaction instruction to begin a transaction comprising a sequence of instructions, wherein the... |
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US20080147949 |
Control microcomputer verification device and vehicle-mounted control device
The present invention offers an advanced control software verification technology, particularly, an assertion-based verification technology, by providing a control microcomputer verification... |
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US20090235004 |
Message Signal Interrupt Efficiency Improvement
A system and method for improving the efficiency of Message Signal Interrupts (MSI) in computer systems. The system utilizes the unused memory addresses in the MSI data payload to identify MSI... |
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US20090049220 |
INTERRUPT-RELATED CIRCUITS, SYSTEMS, AND PROCESSES
An electronic interrupt circuit includes an interrupt-related input line (4235), a security-related status input line (4236), a context-related status input line (4237), and a conversion circuit... |
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US20140189185 |
INTERRUPT MONITORING SYSTEM AND COMPUTER SYSTEM
An interrupt monitoring apparatus includes a storage that stores a given threshold that corresponds to an external interrupt notification; a measuring circuit that measures time that elapses from... |
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US20090070615 |
Multiple power supply management scheme in a power over ethernet (POE) system
An apparatus and method is disclosed to manage multiple power supplies in a Power over Ethernet (PoE) communication system. The PoE communication system provides PoE to one or more powered devices... |
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US20090307509 |
DYNAMIC CPU VOLTAGE REGULATOR PHASE SHEDDING
A voltage regulator phase shedding system includes one or more subsystems to receive a system management interrupt (SMI), gather processor utilization information, determine whether to adjust a... |
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US20140047151 |
INTERRUPT PROCESSING UNIT FOR PREVENTING INTERRUPT LOSS
Techniques are disclosed relating to systems that allow sending and receiving of interrupts between processing elements. In various embodiments, a system includes an interrupt processing unit that... |
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US20140223062 |
NON-AUTHORIZED TRANSACTION PROCESSING IN A MULTIPROCESSING ENVIRONMENT
A protocol for executing the instructions of a non-authorized transaction on the same processor in a multiprocessor environment is provided. A first instruction of a non-authorized transaction... |
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US20080162764 |
PROCESSING METHOD AND PROCESSING DEVICE FOR A HARDWARE INTERRUPT
The present invention discloses a processing device and a processing method for a hardware interrupt, for processing the sharing interrupt. The processing method for the hardware interrupt... |
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US20090172231 |
Data processing device and bus access control method therein
A data processing device includes a computing circuit that accesses a peripheral device connected to through a internal bus, an internal bus connection circuit that is provided between the... |
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US20100174842 |
Effectively Mixing Real-Time Software with a Non-Real-Time Operating System
This disclosure describes a processor system that allows non-real time code to execute normally, while permitting a real time interrupt in hardware or software to execute with minimal added latency. |
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US20080288696 |
DEVICE WITH A PROCESSOR AND A PERIPHERAL UNIT AND METHOD FOR GENERATING AN ACKNOWLEDGMENT SIGNAL
A device is provided that includes a processor, a peripheral unit, and a first logic, and to a method for generating an acknowledgment signal. The processor is clocked by a processor clock signal,... |
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US20100153606 |
APPROACHES FOR MEETING SMI DURATION LIMITS BY TIME SLICING SMI HANDLERS
Approaches that allow the context of an SMI task to be saved between SMIs. Upon entering an SMI handler for a task, a new task context stack is created. Thereafter, the SMI handler uses the task... |
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US20150234640 |
System and Method for Isolating I/O Execution via Compiler and OS Support
Embodiments are provided for isolating Input/Output (I/O) execution by combining compiler and Operating System (OS) techniques. The embodiments include dedicating selected cores, in multicore or... |
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US20090327554 |
SYNCHRONIZING PROCESSORS WHEN ENTERING SYSTEM MANAGEMENT MODE
A system to synchronize processors includes one or more subsystems to receive an interrupt command, instruct a plurality of processors to enter an entry synchronization loop of an interrupt... |
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US20130007325 |
SECURE HANDLING OF INTERRUPTED EVENTS
Various embodiments of this disclosure may describe method, apparatus and system for reducing system latency caused by switching memory page permission views between programs while still... |
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US20130111092 |
SYSTEM AND METHOD FOR ADJUSTING POWER USAGE TO REDUCE INTERRUPT LATENCY
A system and method are described for warming a processor from a low power state in anticipation of a time critical interrupt. For example, one embodiment of a method comprises: detecting that a... |
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US20100070668 |
INTERRUPT CONTROL APPARATUS, INTERRUPT CONTROL SYSTEM, INTERRUPT CONTROL METHOD, AND INTERRUPT CONTROL PROGRAM
An interrupt control unit provides controls on an interrupt from an accelerator to a CPU based on a packet transmitted to or received from a controlled object. The interrupt control unit includes:... |
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US20150120978 |
INPUT/OUTPUT MEMORY MAP UNIT AND NORTHBRIDGE
The present invention provides for page table access and dirty bit management in hardware via a new atomic test[0] and OR and Mask. The present invention also provides for a gasket that enables... |
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US20090327556 |
Processor Interrupt Selection
Processor selection procedures are described. In an implementation, one or more computer-readable media comprise instructions that are executable to cause a processor executing the instructions to... |
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US20090327555 |
Processor Interrupt Determination
Processor interrupt determination procedures are described. In an implementation, one or more computer-readable media comprise instructions that are executable by a computer to determine, based on... |
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US20130019042 |
MECHANISM TO SAVE SYSTEM POWER USING PACKET FILTERING BY NETWORK INTERFACE
A network interface that connects a computing device to a network may be configured to process incoming packets and determine an action to take with respect to each packet, thus decreasing... |
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US20120173782 |
METHOD AND SYSTEM FOR MANAGING SLEEP STATES OF INTERRUPT CONTROLLERS IN A PORTABLE COMPUTING DEVICE
A method and system for managing sleep states of one or more interrupt controllers of processors contained within a portable computing device are described. The method includes a processor... |
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US20150143089 |
SYSTEM PERFORMANCE ENHANCEMENT WITH SMI ON MULTI-CORE SYSTEMS
Mechanisms for providing enhanced system performance and reliability on multi-core computing devices are discussed. Embodiments use modified hardware and/or software so that when a System... |
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US20090070511 |
PROCESSOR SELECTION FOR AN INTERRUPT IDENTIFYING A PROCESSOR CLUSTER
In some embodiments, an apparatus includes processor selection logic to receive logical destination identification numbers that are associated with interrupts each having a processor cluster... |
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US20090198850 |
PROCESSOR, ELECTRONIC APPARATUS, INTERRUPTION CONTROL METHOD AND INTERRUPTION CONTROL PROGRAM
A processor 1 provided with a plurality of cores, an interrupt operation dedicated core 20 which is used only for an interrupt operation; a normal core 11 to 1n which outputs an interrupt request... |
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US20090177829 |
INTERRUPT REDIRECTION WITH COALESCING
An interrupt redirection and coalescing system for a multi-processor computer. Devices interrupt a processor or group of processors using pre-defined message address and data payloads communicated... |
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US20070260794 |
METHOD OF TRANSITIONING BETWEEN ACTIVE MODE AND POWER-DOWN MODE IN PROCESSOR BASED SYSTEM
A method of transitioning between an active mode and a power-down mode in a processor-based system includes saving a state of the active mode, detecting the occurrence of one or more interrupt... |
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US20150220464 |
DYNAMIC INTERRUPT STACK PROTECTION
A protection unit of an interrupt stack accessible by a CPU controlled by one software program, for storing and removing stack frame(s), the stack protection unit being coupleable to the stack and... |
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US20150227476 |
REDUCING LATENCY IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS LINK
A method and system are described for reducing latency in a peripheral component interconnect express (PCIe) link between a host and an endpoint. In the described embodiments, an interrupt is... |
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US20090037932 |
MECHANISM FOR BROADCASTING SYSTEM MANAGEMENT INTERRUPTS TO OTHER PROCESSORS IN A COMPUTER SYSTEM
A computer system includes a system memory, a plurality of processor cores, and an input/output (I/O) hub that may communicate with each of the processor cores. In response to detecting an... |
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US20130166805 |
INTERRUPT CAUSE MANAGEMENT DEVICE AND INTERRUPT PROCESSING SYSTEM
A peripheral device sends an interrupt generation notification to a bus bridge. The bus bridge receives the interrupt generation notification, transfers the received interrupt generation... |
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US20140173150 |
SYSTEM ON CHIP, METHOD OF OPERATING THE SAME, AND APPARATUS INCLUDING THE SAME
A method of operating a system on chip (SoC) includes calculating a first residence time indicating an amount of time that at least one task resides in an execution queue in the SoC, wherein the... |
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US20130185469 |
INTERRUPT SIGNAL ACCEPTING APPARATUS AND COMPUTER APPARATUS
An interrupt signal accepting apparatus manages two OSs, relates devices sharing the same interrupt number respectively with an OS caused to perform an interrupt processing and an interrupt... |
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US20090138740 |
METHOD AND COMPUTER DEVICE CAPABLE OF DEALING WITH POWER FAIL
A method capable of dealing with a power fail is adapted for a control board with power thereof supplied from a power supply. The control board has a processor and a memory disposed thereon. The... |
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US20100191887 |
Monitoring Interrupt Acceptances in Guests
In one embodiment, an interrupt acceptance control circuit is provided. The interrupt acceptance control circuit may monitor one or more guest interrupt controllers in a system in response to an... |
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US20100050184 |
MULTITASKING PROCESSOR AND TASK SWITCHING METHOD THEREOF
A multitasking processor and a task switching method thereof are provided. The task switching method includes following steps. A first task is executed by the multitasking processor, wherein the... |
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US20110106994 |
METHOD AND APPARATUS FOR QUALIFYING COLLECTION OF PERFORMANCE MONITORING EVENTS BY TYPES OF INTERRUPT WHEN INTERRUPT OCCURS
A method, apparatus, and computer instructions for qualifying events by types of interrupt when interrupt occurs in the processor of a data processing system. A programmable performance monitoring... |
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US20110040915 |
FLEXIBLE NOTIFICATION MECHANISM FOR USER-LEVEL INTERRUPTS
A method includes delivering a user-level interrupt message indicative of a user-level interrupt to one or more recipients according to a user-level interrupt delivery configuration selected from... |
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US20140136745 |
METHOD AND APPARATUS FOR ALLOCATING INTERRUPTS IN A MULTI-CORE SYSTEM
An apparatus and a method for allocating interrupts in a multi-core system are provided. According to an embodiment, an interrupt control register unit records the interrupt processing capacity of... |
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US20080307248 |
Cpu Clock Control Device, Cpu Clock Control Method, Cpu Clock Control Program, Recording Medium, and Transmission Medium
A program execution time determining portion determines an execution start time and a processing volume per unit time of a program in such a manner that a processing volume necessary to execute... |
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US20080114917 |
Optical disc recording and reproducing apparatus
A predetermined power failure recovery process is carried out when power failure recovery data is determined to be present in a flash ROM when a power supply is turned on after a power failure.... |
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US20100057967 |
RECORDING MEDIUM WITH LOAD DISTRIBUTION PROGRAM RECORDED THEREIN AND LOAD DISTRIBUTION APPARATUS
A recording medium with a load distribution program recorded therein for causing a computer system to execute the following processing includes: acquiring, at every first timing, a processor load... |
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US20100274940 |
INTERRUPT COALESCING FOR OUTSTANDING INPUT/OUTPUT COMPLETIONS
In a computer system, a method of controlling coalescence of interrupts includes dynamically basing a current level of interrupt coalescing upon a determination of outstanding input/output (I/O)... |