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US20090307433 |
Cache memory system
Systems and methods for pre-fetching data are disclosed that use a cache memory for storing a copy of data stored in a system memory and mechanism to initiate a pre-fetch of data from the system...
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US20090307403 |
SYSTEM FOR EXECUTING SYSTEM MANAGEMENT INTERRUPTS AND METHODS THEREOF
An information handling system includes a first processor device to execute a handler in response to a system management interrupt (SMI). While the first processor device executes the SMI handler,...
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US20090307511 |
PORTABLE ELECTRONIC DEVICES WITH POWER MANAGEMENT CAPABILITIES
An electronic device may operate in standby and active modes. A headset may be coupled to the electronic device. The electronic device may have audio codec circuitry. The audio codec circuitry may...
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US20090300250 |
System and Method for Virtualizing Processor and Interrupt Priorities
Dispatching of interrupts to a processor is conditionally suppressed, that is, only if an old priority value and a new priority value are either both less than or both greater than a maximum...
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US20090300249 |
SELECTIVE MISR DATA ACCUMULATION DURING EXCEPTION PROCESSING
A plurality of test points are located at predetermined circuit nodes in a processing system. Test code which includes a set of software-controllable interrupts is executed using a multiple input...
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US20090300657 |
INTELLIGENT MENU IN A COMMUNICATION DEVICE
The invention relates to a method for launching an application in a communication device, comprising the steps of detecting, in the communication device, one or more terms during communication...
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US20090293065 |
EMULATING A HOST ARCHITECTURE IN GUEST FIRMWARE
Systems and methods provide for emulating a host architecture in guest firmware. One aspect of the systems and methods comprises determining whether an emulated instruction would cause a transition...
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US20090292846 |
METHOD OF INTERRUPT SCHEDULING
There is provided a method of interrupt scheduling. The method comprises: without allowing a target process woken up when an interrupt occurs to enter into a ready queue, directly comparing the...
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US20090282179 |
METHOD AND SYSTEM OF GROUPING INTERRUPTS FROM A TIME-DEPENDENT DATA STORAGE MEANS
A method of grouping interrupts from a time-dependent data storage means in accordance with the types of the interrupts, the method comprising the steps of providing each part of the data storage...
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US20090271548 |
INTERRUPT RESPONSE CONTROL APPARATUS AND METHOD THEREFOR
An interrupt response control apparatus comprises an input for receiving an interrupt request. A response monitoring module is arranged to detect performance of a first function in response to the...
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US20090265721 |
INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND COMPUTER PROGRAM
An information processing apparatus includes a device that performs data processing; and processors, each processor including a device driver corresponding to the device. A device driver set in...
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US20090254765 |
METHOD FOR POWER MANAGEMENT FOR COMPUTER SYSTEM
The invention provides a method for power management for a computer system. In one embodiment, the computer system comprises a system controller, a chipset, and a battery coupled to the chipset via...
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US20090248932 |
BI-DIRECTIONAL SINGLE CONDUCTOR INTERRUPT LINE FOR COMMUNICATION BUS
A bi-directional single conductor interrupt line is used in conjunction with a master only initiated data communication bus, to allow a slave device to submit a slave service request to a master...
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US20090235056 |
RECORDING MEDIUM STORING PERFORMANCE MONITORING PROGRAM, PERFORMANCE MONITORING METHOD, AND PERFORMANCE MONITORING DEVICE
A performance monitoring device has an interrupt detection unit that detects generation of an interrupt process to be executed by a processor in accordance with TLB entry invalidation executed in...
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US20090222673 |
SYSTEM FOR CONTROLLING ACCESS AND DISTRIBUTION OF DIGITAL PROPERTY
Digital data protection is provided by a processor running an operating system programmed to generate one or more interrupts; an access mechanism detects one or more interrupts at or below a BIOS...
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US20090216827 |
Virtual Sensor
The object of the present invention is to enable to utilize the sensor(s) in the manner that is optimized for the application, as well as easily. According to one aspect of the present invention,...
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US20090216961 |
MULTI-PORT SEMICONDUCTOR MEMORY DEVICE FOR REDUCING DATA TRANSFER EVENT AND ACCESS METHOD THEREFOR
A multiport semiconductor memory device includes at least three port units coupled respectively to corresponding processors, a shared memory area accessed in common by the processors through the...
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US20090216928 |
SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A NEW QUIESCE STATE
A system, method and computer program product for providing a new quiesce state. The method includes receiving a quiesce request at a system controller from an initiating processor. The quiesce...
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US20090210599 |
Electronic Circuit
An electronic circuit comprises a bus ( 300 ), a processor unit ( 100 ), and an operating sector ( 400 ). The operating sector ( 400 ) includes a first operating unit ( 421 ), a second operating...
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US20090204739 |
Interruptible write block and method for using same
A disclosed embodiment is an interruptible write block comprising a primary register having an input coupled to an input of the interruptible write block, a secondary register having an input...
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US20090204978 |
SYNCHRONIZING SPLIT USER-MODE/KERNEL-MODE DEVICE DRIVER ARCHITECTURE
A device driver includes a kernel mode and a user-mode module. The device driver may access device registers while operating in user-mode to promote system stability while providing a low-latency...
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US20090193216 |
Method and Apparatus for Hardware Enforced Virtual Sequentiality
A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a...
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US20090193168 |
INTERRUPT MITIGATION ON MULTIPLE NETWORK ADAPTERS
A method, information processing system, and computer readable medium, mitigate processor assignments. A first processor in a plurality of processors is assigned to a first communication port in a...
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US20090172227 |
SERIAL ADVANCED TECHNOLOGY ATTACHMENT WRITE PROTECTION: MASS STORAGE DATA PROTECTION DEVICE
A mass storage device protection system may have a mass storage device, a processor configured to generate at least one serial write command signal to the mass storage device via a serial...
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US20090172684 |
SMALL LOW POWER EMBEDDED SYSTEM AND PREEMPTION AVOIDANCE METHOD THEREOF
Provided are a small low power embedded system and a preemption avoidance method thereof. A method for avoiding preemption in a small low power embedded system includes fetching and running a...
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US20090172302 |
Information Processing Apparatus, Information Processing Method, and Program
The present invention relates to an information processing apparatus, an information processing method, and a program capable of simplifying an interrupt processing and reducing a time necessary to...
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US20090172229 |
METHODS FOR SELECTING CORES TO EXECUTE SYSTEM MANAGEMENT INTERRUPTS
A method includes directing a system management interrupt to a processor core from a plurality of processor cores of a computing device for handling based upon core load-sharing considerations. A...
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US20090164814 |
Hardware driven processor state storage prior to entering a low power mode
A data processing apparatus comprising: a processor for processing data, said processor comprising memory interface logic for controlling transfer of data to a memory, said processor being powered...
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US20090158068 |
REDUCING CORE WAKE-UP LATENCY IN A COMPUTER SYSTEM
A power control unit (PCU) may reduce the core wake-up latency in a computer system by concurrently waking-up the remaining cores after the first core is woken-up. The power control unit may detect...
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US20090144589 |
DEVICE AND METHOD FOR CONTROLLING AN EXECUTION OF A DMA TASK
A method for controlling an execution of a first DMA task, the method includes comprises monitoring an execution of the first DMA task, the method characterized by including defining a first DMA...
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US20090125912 |
High performance memory and system organization for digital signal processing
An innovative approach for constructing optimum, high-performance, efficient DSP systems may include a system organization to match compute execution and data availability rate and to organize DSP...
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US20090119468 |
SYSTEMS, METHODS, AND APPARATUSES FOR ERASING MEMORY ON WIRELESS DEVICES
A wireless device having a memory is provided. The memory or a protected portion of the memory is subject to a hard erasure of the memory vs. a soft erasure of the memory if a plurality of sensors...
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US20090113100 |
Logic gateway circuit for bus that supports multiple interrupt request signals
A logic gateway circuit is provided for a bus to support multiple interrupt request signals, including an output OR gate having a plurality of input terminals and an interrupt request signal output...
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US20090089470 |
INTERRUPT BALANCING FOR MULTI-CORE AND POWER
A method and apparatus for balancing power savings and performance in handling interrupts is herein described. When an amount of interrupt activity is above a threshold, a performance mode of...
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US20090077292 |
DATA PROCESSING APPARATUS, METHOD OF CONTROLLING TERMINATION VOLTAGE OF DATA PROCESSING APPARATUS, AND IMAGE FORMING APPARATUS
A processing unit carries out a predetermined data processing on the data in a storage unit. The storage unit is connected to the processing unit with a plurality of connecting lines. A voltage...
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US20090070509 |
Method of detecting and protecting falling portable computer hard disk through software monitoring driver
In a method of detecting and protecting a hard disk of a falling portable computer, a falling sensor detects a falling state of a portable computer and sends an interrupt signal to a keyboard...
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US20090063725 |
Direct memory access system
A direct memory access (DMA) system is disclosed herein. The DMA system includes a controller and an interrupt processing unit. The controller is coupled to a first module and a second module for...
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US20090055609 |
SYSTEMS FOR DYNAMICALLY RESIZING MEMORY POOLS
There are disclosed systems and computer program products for dynamically resizing memory pools used by database management systems. In one aspect, if a decrease in allocation to the memory pool is...
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US20090013117 |
SYSTEM AND METHOD FOR GENERATING INTERRUPT
A system and a method for generating an interrupt are provided. In the interrupt generating method, a time-out mechanism is executed by a second network component of a computer system after a...
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US20080307140 |
SIDEBAND SIGNAL FOR USB WITH INTERRUPT CAPABILITY
The invention provides for a sideband signal for the USB that has real-time interrupt capabilities. A system and method for hardware detection of an interrupt signal provides for the ability to...
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US20080288692 |
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MICROCOMPUTER
It is intended to improve the efficiency of request retransmission. A high-speed serial interface block is provided which enables split-transaction communication performed through the issuing of a...
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US20080276026 |
SELECTIVE DEACTIVATION OF PROCESSOR CORES IN MULTIPLE PROCESSOR CORE SYSTEMS
A method includes applying a voltage to a first processor core of a plurality of processor cores to deactivate the first processor core, the voltage less than a retention voltage of the first...
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US20080270661 |
Interruption Management
The present invention relates to a method, system 1 and/or software 16 for handling interruptions. Upon interruption, a user can place an indicator 60 on their screen. The applications are...
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US20080244136 |
Integrated Circuit and Method For Transaction Abortion
An integrated circuit having a plurality of processing modules (M, S) and an interconnect means (N) for coupling said plurality of processing modules (M, S) and for enabling a device-level...
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US20080235424 |
Method and apparatus for performing interrupt coalescing
In one embodiment, the invention includes a controller that interrupts a CPU based on a counter that uses a decrement step which may increase as high priority data packets are received by the...
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US20080228979 |
Trigger core
A method to detect an event between a data source and a data sink using a trigger core is described herein. The method comprises monitoring control lines and an associated data stream for a...
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US20080222333 |
Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response
Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution...
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US20080215787 |
Method and System for Processing Status Blocks Based on Interrupt Mapping
Certain aspects of a method and system for processing status blocks based on interrupt mapping may be disclosed. Exemplary aspects of the method may include determining whether a particular status...
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US20080183931 |
Method, system and device for handling a memory management fault in a multiple processor device
A method or device handles memory management faults in a device having a digital signal processor (“DSP”) and a microprocessor. The DSP includes a memory management unit (“DSP MMU”) to...
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US20080183930 |
Profiling collector for computer system
In one embodiment a computer system comprises one or more processors and a memory module communicatively connected to the one or more processors. The memory module comprises logic instructions...
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