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US20090037638 |
Backend-connected storage system
A switch device is interposed between a controller and a storage device in a storage system. One or more physical ports among the plurality of physical ports that the switch device has are physical...
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US20120131235 |
USING A TABLE TO DETERMINE IF USER BUFFER IS MARKED COPY-ON-WRITE
A method, system and computer program product for determining if a buffer is marked copy-on-write. A user applications selects a buffer in user space to store data involved in a write/read...
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US20110320638 |
ENABLE/DISABLE ADAPTERS OF A COMPUTING ENVIRONMENT
An adapter is enabled for use. The enabling includes assigning one or more address spaces to the adapter, based on a request. For each address space assigned to the adapter, a corresponding device...
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US20100100679 |
Embedded scale-out aggregator for storage array controllers
Methods and systems for dynamic storage tiering may comprise: discovering one or more remote virtual drives associated with one or more remote storage arrays; advertising one or more local virtual...
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US20100332720 |
Direct Memory Access and Super Page Swapping Optimizations For A Memory Blade
A system and method is illustrated for identifying an Input/Output (I/O) driver module, using a hypervisor, to receive a read command to read a virtual memory page from a remote memory location....
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US20080052507 |
Multi-Partition USB Device that Re-Boots a PC to an Alternate Operating System for Virus Recovery
A multi-partition Universal Serial Bus (USB) device has a flash memory with multiple partitions of storage. Some partitions are for different operating systems and store OS images. Another...
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US20110060853 |
SYSTEM, METHOD, AND DEVICE FOR ROUTING CALLS USING A DISTRIBUTED MOBILE ARCHITECTURE
Methods and devices for routing communications between distributed mobile architecture (DMA) servers using DMA gateways are disclosed. Communications information is received at a first DMA gateway...
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US20090150894 |
Nonvolatile memory (NVM) based solid-state disk (SSD) system for scaling and quality of service (QoS) by parallelizing command execution
A method for scaling a SSD system which includes providing at least one storage interface and providing a flexible association between storage commands and a plurality of processing entities via...
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US20070162646 |
Direct memory access devices and method based timer system
The direct memory access device and method of the present invention uses an event calendar, an expired event queue of a fixed size, a calendar scanner, and an event mover. The event calendar stores...
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US20060064517 |
Event-driven DMA controller
A DMA memory controller includes a program module operable to receive and execute instructions comprising instructions to perform multiple DMA transfers. The multiple DMA transfers are triggered by...
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US20100064071 |
DMA device having plural buffers storing transfer request information and DMA transfer method
A Direct Memory Access (DMA) device includes a first buffer which holds a first transfer information required for a first transfer request, and a second buffer which holds a second transfer...
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US20100161844 |
DMA compliance by remapping in virtualization
Methods, systems, apparatuses and program products are disclosed for managing DMA compliance by remapping in hypervisor and hypervisor-related environments.
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US20060026310 |
Computer system having an I/O module directly connected to a main storage for DMA transfer
A computer system includes a CPU (Central Processing Unit) and a main storage interconnected by a bus to the CPU. The I/O module for transferring received data and data to be transmitted to and...
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US20100057949 |
CIRCUITS, SYSTEMS, AND METHODS TO INTEGRATE STORAGE VIRTUALIZATION IN A STORAGE CONTROLLER
Methods and systems for improved performance in virtualized storage systems. Features and aspects hereof provide for a virtualization circuit integrated in each storage controller of a storage...
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US20090094388 |
DMA Completion Mechanism
An apparatus and a computer program product are provided for completing a plurality of (direct memory access) DMA commands in a computer system. It is determined whether the DMA commands are...
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US20080201495 |
HANDLING DMA OPERATIONS DURING A PAGE COPY
A memory controller provides page copy logic that assures data coherency when a DMA operation to a page occurs during the copying of the page by the memory controller. The page copy logic compares...
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US20100082848 |
INCREASING AVAILABLE FIFO SPACE TO PREVENT MESSAGING QUEUE DEADLOCKS IN A DMA ENVIRONMENT
Embodiments of the invention may be used to manage message queues in a parallel computing environment to prevent message queue deadlock. A direct memory access controller of a compute node may...
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US20060259658 |
DMA reordering for DCA
In an embodiment, an apparatus and method include reordering direct cache access (DCA) and non-DCA transfers so that DCA transfers are last transactions and therefore closer to an interrupt than...
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US20060235999 |
Doorbell mechanism
Provided are techniques for writing doorbell information. In accordance with certain techniques, one or more protection domains are created. One or more data structures are created, wherein each of...
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US20090006664 |
Linked DMA Transfers in Video CODECS
A new mechanism submits multiple DMA requests that are becoming more common in the newer video codec standards. This feature improves system performance and allows bus accesses to be more...
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US20070168579 |
DMA transfer and hardware acceleration of PPP frame processing
PPP frame encapsulation of IP frames—including FCS calculation, character escaping, and HDLC flag insertion—is performed by hardware acceleration circuits within a DMA module as part of a DMA tra...
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US20090287873 |
SEMICONDUCTOR INTEGRATED CIRCUIT, SYSTEM DEVICE INCLUDING SEMICONDUCTOR INTEGRATED CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT CONTROL METHOD
A disclosed semiconductor integrated circuit interfaces an external circuit and a host for controlling the external circuit and obtains data used to interface the external circuit and the host from...
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US20080005387 |
Semiconductor device and data transfer method
A semiconductor device and data transfer method capable of efficient DMA transfer processing. The device comprises: a sector buffer which temporarily stores data during transfer, the buffer having...
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US20090006662 |
OPTIMIZED COLLECTIVES USING A DMA ON A PARALLEL COMPUTER
Optimizing collective operations using direct memory access controller on a parallel computer, in one aspect, may comprise establishing a byte counter associated with a direct memory access...
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US20050154801 |
Programming system and method for a video network
In a signal processing system, a programming system and method for a video network are provided. An event may trigger an RDMA controller to execute current instructions in a register update list....
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US20050240726 |
Synergistic hybrid disk drive
Two or more disk drives communicate directly with each other to establish a synergistic hybrid disk drive (SHDD) that supplies data to a computer system faster and more reliably than would be...
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US20110321158 |
GUEST ACCESS TO ADDRESS SPACES OF ADAPTER
An authorization mechanism allows a host executing a guest operating system to grant permission for the guest to directly access an adapter function's address spaces without host intervention. This...
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US20050235072 |
Data storage controller
Tags are associated with commands in a data storage system. Through the use of these tags, routing and processing of commands and data associated with the commands may be handled by software and/or...
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US20110153873 |
METHOD AND DEVICE FOR DETECTING ERRONEOUS TRANSFERS FOR MICROCONTROLLER OR MICROPROCESSOR WITH A VIEW TO GUARANTEEING PARTITIONING
A method and a device for the detection of erroneous or inopportune transactions of any entity of a microprocessor or microcontroller includes programming counters internal or external to the...
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US20080168190 |
Input/Output Tracing in a Protocol Offload System
I/O tracing is implemented in a system in which an I/O device is configured for protocol offload. A data unit having headers and payload is replicated and the replicated unit sent to the end node...
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US20070162648 |
DMA Controller With Self-Detection For Global Clock-Gating Control
A standby self-detection mechanism in a DMA controller which reduces the power consumption by dynamically controlling the on/off states of at least one clock tree driven by global clock-gating...
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US20080104337 |
RDMA copy-on-write
In an embodiment of the invention, an apparatus and method for Remote Direct Access Memory (RDMA) copy-on-write perform the steps including: marking a page of a first application as copy-on-write...
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US20050132149 |
Spatial-to-temporal data translation and scheduling and control
An organization of at least one content of at least one spatial data storage system is determined. A schedule of content transmission in response to the organization of the at least one content of...
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US20080114937 |
Mapping a computer program to an asymmetric multiprocessing apparatus
A computer implemented tool is provided for assisting in the mapping of a computer program to an asymmetric multiprocessing apparatus 2 incorporating an asymmetric memory hierarchy formed of a...
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US20070174505 |
DMA access systems and methods
Methods and systems for performing direct memory access (DMA) transfers are described. An invalidate queue (or other storage device) contains an entry associated with a DMA transfer in progress. If...
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US20060069818 |
Synchronizing direct memory access and evacuation operations in a computer system
A computer-implemented method for performing an evacuation request pertaining to a set of memory pages. The method includes inhibiting new DMA operations on a range of memory, the range of memory...
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US20100017650 |
NON-VOLATILE MEMORY DATA STORAGE SYSTEM WITH RELIABILITY MANAGEMENT
A non-volatile memory data storage system, comprising: a host interface for communicating with an external host; a main storage including a first plurality of flash memory devices, wherein each...
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US20080263235 |
Device-to-Device Sharing of Digital Media Assets
Apparatus, a method, or an electronic device may be provided. Media and a data structure encoded on the media are each provided, to hold one or more digital media assets (DMAs). One or more share...
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US20080065855 |
DMAC Address Translation Miss Handling Mechanism
A memory management unit (MMU) performs address translation and protection using a segment table and page table model. Each DMA queue entry may include a MMU-miss dependency flag. The DMA issue...
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US20060221990 |
Hiding system latencies in a throughput networking system
A method for addressing system latency within a network system which includes providing a network interface and moving data within each of the plurality of memory access channels independently and...
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US20060195628 |
System and method for DMA transfer between FIFOs
A system for DMA transfer includes a CPU core having a DMA function, a first macro including a FIFO having a first bit width, and a second macro including a FIFO having a second bit width narrower...
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US20060026307 |
Method for direct memory access, related architecture and computer program product
A method of exchanging data within a direct memory access (DMA) arrangement including a plurality of IP blocks (A, B, C) includes the step of associating with the IP blocks (A, B, C) respective DMA...
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US20050114559 |
Method for efficiently processing DMA transactions
The data rate at which DMA transactions are processed by a General Purpose Computer System can be significantly improved by directing housekeeping type transactions directly to the CPU bus and by...
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US20080005384 |
Hard disk drive progressive channel interface
Hard disk drive progressive channel interface. A novel approach is presented by which the interface between a channel circuitry and a controller circuitry, such as those which can be implemented...
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US20070186016 |
DEVICE FOR TRANSFERRING DATA ARRAYS BETWEEN BUSES AND SYSTEM FOR MAC LAYER PROCESSING COMPRISING SAID DEVICE
A device for transferring data arrays between at least two buses, the device comprising storage means for storing at least one data array, a first input/output interface for transferring data...
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US20050216614 |
Microcomputer having instruction RAM
A microcomputer comprises an instruction RAM temporally storing a program transferred from an external memory, a CPU reading out the program from the instruction RAM via a dedicated fetch bus and...
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US20080209085 |
SEMICONDUCTOR DEVICE AND DMA TRANSFER METHOD
A semiconductor device includes a plurality of resources for performing DMA transfer and a DMA controller, wherein the plurality of resources each include a transfer setting register
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US20120036288 |
SYSTEMS AND METHODS FOR USING A SHARED BUFFER CONSTRUCT IN PERFORMANCE OF CONCURRENT DATA-DRIVEN TASKS
Disclosed herein are techniques to execute tasks with a computing device. A first task is initiated to perform an operation of the first task. A buffer construct that represents a region of memory...
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US20070022225 |
Memory DMA interface with checksum
A system and method comprising a direct memory access (DMA) circuit configured to directly access a memory, and a checksum adder configured to determine a checksum for data transferred between the...
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US20120124249 |
Method Of Data Communications With Reduced Latency
Data communications with reduced latency, including: writing, by a producer, a descriptor and message data into at least two descriptor slots of a descriptor buffer, the descriptor buffer...
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