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US20120011187 
PARALLEL REDUNDANT DECIMAL FUSEDMULTIPLYADD CIRCUIT
A circuit for performing a floatingpoint fusedmultiplyadd (FMA) calculation of a×b±c. The circuit includes (i) a partial product generation module having (a) a multiples generator unit c...


US20140280426 
INFORMATION RETRIEVAL USING SPARSE MATRIX SKETCHING
Embodiments of the invention include method of approximating a matrix of data using sparse matrices which includes receiving a first matrix and generating a second matrix based on the first matrix...


US20130080489 
SYSTEMS AND METHODS FOR DETERMINING RESPIRATION INFORMATION FROM A PHOTOPLETHYSMOGRAPH
A patient monitoring system may receive a photoplethysmograph (PPG) signal including samples of a pulse waveform. A plurality of morphology metric signals may be generated from the PPG signal. The...


US20120078993 
ReducedLevel Two's Complement Arithmetic Unit
A processor includes a two's complement arithmetic unit that reduces a level of complexity in the critical path by eliminating the addition of the “1” to the carry in of the two's complement ari...


US20130110897 
DIGITAL FILTER HAVING IMPROVED ATTENUATION CHARACTERISTICS
A digital filter having improved attenuation characteristics is disclosed. The disclosed performs upsampling of model filter response by applying a sampling kernel scaled by a sampling constant....


US20130339414 
SYSTEM AND METHOD TO COMPUTE NARROW BOUNDS ON A MODAL INTERVAL POLYNOMIAL FUNCTION
A computer executable method of processing a representation of a modal interval polynomial is provided. A representation of a modal interval polynomial is generally provided as input, more...


US20120166503 
METHOD FOR FULLY ADAPTIVE CALIBRATION OF A PREDICTION ERROR CODER
Method for fully adaptive calibration of a prediction error coder, comprising a first step of initialization; a second step of reception and accumulation of blocksize data samples wherein for each...


US20100318592 
Multiplicative Division Circuit With Reduced Area
The technology is a division circuit with decreased circuit area. An embodiment includes an integrated circuit implementing multiplicative division of a dividend input and a divisor input. The...


US20140188966 
Floatingpoint multiplyadd unit using cascade design
A floatingpoint fused multiplyadd (FMA) unit embodied in an integrated circuit includes a multiplier circuit cascaded with an adder circuit to produce a result A*C+B. To decrease latency, the FMA...


US20130246497 
ADAPTIVE PRECISION ARITHMETIC UNIT FOR ERROR TOLERANT APPLICATIONS
Two processtolerant arithmetic circuit architectures are implemented to develop functional blocks for errortolerant applications such as FIR filters and FFT blocks. The resulting blocks may...


US20110302228 
Calculator with Dynamic Computation Environment
A dynamic computational environment may create, in response to user input, a plurality of mathematical expressions. In the dynamic computational environment, a change made to any one of the...


US20140214910 
Implementing Modified QR Decomposition in Hardware
System and method for computing QR matrix decomposition and inverse matrix R−1. A circuit is configured to implement a QR decomposition of a matrix A into two matrices Q and R using a Modified G...


US20140344320 
METHOD FOR EVALUATING THE SOLUTION TO A MULTICRITERIA OPTIMIZATION PROBLEM
Solving a multidimensional multicriteria optimization problem is difficult because the correlations and dependencies between solutions, target functions, and variation variables can be detected...


US20140207839 
Spatial Arithmetic Method of Integer Factorization
A computer system represents numbers as threedimensional relations, which may be represented as collections of points in threedimensional space. The threedimensional representations may use...


US20140082039 
Interleaved Method for Parallel Implementation of the Fast Fourier Transform
The present invention generally relates to a method for computing a Fast Fourier Transform (FFT). In one embodiment, the present invention relates to an interleaved method for computing a Fast...


US20120278374 
Decimal FloatingPoint Quantum Exception Detection
A system and method for detecting decimal floating point data processing exceptions. A processor accepts at least one decimal floating point operand and performs a decimal floating point operation...


US20100299381 
Algorithm for the Adaptive Infinite Impulse Response Filter
A new method to adjust the parameters of an adaptive Infinite Impulse Response (IIR) filter is suggested. The method adjusts the set of parameters of the pole polynomial of the filter. The...


US20140067896 
Universe has an End
The “Big Bung!” was not at the beginning of Universe!


US20120084335 
METHOD AND APPARATUS OF PROCESSING FLOATING POINT NUMBER
A method and apparatus of processing floating point number(s) is provided. The method which processes a plurality of first floating point numbers each having a mantissa and an exponent includes:...


US20140075410 
METHODS AND SYSTEMS FOR DETERMINING A FORMULA
In a method to help a user determine a formula, (e.g., a fact, rule, or principle expressed in scientific, mathematical, technical, etc. symbols), a user may input an indication of the formula in...


US20110125466 
ComputerImplemented Systems And Methods For Determining SteadyState Confidence Intervals
Computerimplemented systems and methods for estimating confidence intervals for output generated from a computer simulation program that simulates a physical stochastic process. A plurality of...


US20140280430 
Multiplier Circuit with Dynamic Energy Consumption Adjustment
A fixed point multiplier that can be used in mobile computer systems operating under limited power constraints provides a tradeoff between computational accuracy and energy consumption that may be...


US20120179734 
METHOD AND APPARATUS FOR DISCRETE COSINE TRANSFORM/INVERSE DISCRETE COSINE TRANSFORM
Discrete cosine transform/inverse discrete cosine transform method and device are provided. The discrete cosine transform/inverse discrete cosine transform method includes: generating a table index...


US20130046805 
Precision Measurement of Waveforms Using Deconvolution and Windowing
The invention consists of new ways of constructing a Measuring Matrices (MMs) including time deconvolution of Digital Fourier Transforms DFTs. Also, windowing functions specifically designed to...


US20130066933 
METHOD AND APPARATUS FOR DERIVING COMPOSITE TIE METRIC FOR EDGE BETWEEN NODES OF A TELECOMMUNICATION CALL GRAPH
A method for deriving a composite tie metric for an edge between nodes of a telecommunication call graph includes receiving descriptive data with original values for descriptive attributes...


US20110295921 
Hybrid Greatest Common Divisor Calculator for Polynomials
A hybrid greatest common divisor (GCD) calculator analyzes characteristics of polynomials and selects a particular GCD algorithm from multiple available GCD algorithms based on a combination of...


US20110160902 
METHOD AND APPARATUS FOR PRODUCING CUSTOMIZED FOOD BLENDS FOR ANIMALS
A method and apparatus for producing customized food blends for animals includes a food assembler that is in electrical connection with one or more computer systems that provide instructions and...


US20150019606 
Method for evaluating an output of a random generator
A method and an assemblage for checking an output of a random generator are presented. In the method, signatures that are respectively created from a sequence of sampled values are compared with...


US20110191400 
L1 Projections with Box Constraints
Similarities between simplex projection with upper bounds and L1 projection are explored. Criteria for apriori determination of sequence in which various constraints become active are derived, and...


US20140337399 
METHOD OF GENERATING RANDOM NUMBERS III
A system and method of generating uniform and independent random numbers is given by comprising two distinct odd primes that give an odd integer and an even integer, together with by taking an...


US20130173683 
Range Check Based Lookup Tables
Mechanisms for utilizing a reduced lookup table circuit to perform an operation in a data processing device are provided. A first input value is input for selecting a subset of values from the...


US20130173681 
Range Check Based Lookup Tables
Mechanisms for utilizing a reduced lookup table circuit to perform an operation in a data processing device are provided. A first input value is input for selecting a subset of values from the...


US20120047193 
LOCUS SMOOTHING METHOD
The present invention discloses a locus smoothing method, comprising: generating multiple locus points by movement of an object; obtaining corresponding coordinates of the locus points; calculating...


US20110029589 
LOW POWER FIR FILTER IN MULTIMAC ARCHITECTURE
Embodiments of the invention are directed to system and method that enable relatively low power dissipation by scheduling operations of multiply accumulators chain of two or more multiply...


US20120290632 
METHOD OF GENERATING RANDOM NUMBERS II
A method of obtaining uniform and independent random numbers is given 1. by taking two distinct odd primes p1,p2 that give mutually coprime integers, an odd q1=(p1−1)/2 and an even q2=(p2−1)/2, to ...


US20120331023 
INTERACTIVE EXHIBITS
Disclosed in one example is a method for providing an interactive exhibit to a user. The method may include creating plotting instructions for an interactive exhibit based on an exhibit description...


US20120237025 
DEVICE AND METHOD FOR DETERMINING AN INVERSE OF A VALUE RELATED TO A MODULUS
A device for determining an inverse of an initial value related to a modulus, comprising a unit configured to process an iterative algorithm in a plurality of iterations, wherein an iteration...


US20050278407 
Addressing type of asynchronous divider
The present invention relates to an addressing type of asynchronous divider that uses addressing system, which enables an external circuit to receive a divisor and a dividend. Through the process...


US20110289131 
MACHINE DIVISION
Techniques are generally described that include methods, devices, systems and/or apparatus for dividing a numerator by a denominator. Some example methods may include selecting a first numerical...


US20130151576 
APPARATUS AND METHOD FOR ROUNDING A FLOATINGPOINT VALUE TO AN INTEGRAL FLOATINGPOINT VALUE
Processing circuitry is provided to perform an operation FRINT for rounding a floatingpoint value to an integral floatingpoint value. Control circuitry controls the processing circuitry to...


US20100023575 
PREDICTOR
A Predictor is described which is based on a modified RLS (recursive least squares) algorithm. The modifications prevent divergence and accuracy problems when fixed point implementation is used.


US20140122549 
Intermediate Steps Display for a Calculator
This patent is for a device that displays the steps involved in a calculation as well as the answer of the calculation. By doing this you preserve the main benefits of the calculator (speed and...


US20130262550 
MATRIX CALCULATION DEVICE, MATRIX CALCULATION METHOD, AND STORAGE MEDIUM HAVING MATRIX CALCULATION PROGRAM STORED THEREON
A matrix calculation device includes a first partition position display unit configured to distinguishably display a partition position of the one matrix partitioned by the matrix partitioning...


US20110099217 
Method and System for Determining a Quotient Value
A method for determining a quotient value from a dividend value and a divisor value in a digital processing circuit is provided. The method includes computing a reciprocal value of the divisor...


US20060089956 
Classification unit and methods thereof
A classification unit is to process an odd number of inputs in a single instruction cycle by comparing all distinct pairs of inputs and selecting one of the inputs based on the comparisons.


US20140344321 
AUTOMATIC CONTROL SYSTEM AND METHOD FOR A TRUE RANDOM NUMBER GENERATOR
A system for reseeding a pseudo random number generator to generate pseudo random numbers includes a true random number generator generating a true random number, a storage device storing the...


US20140192977 
MUTIPLICATION METHOD AND MODULAR MULTIPLIER USING REDUNDANT FORM RECODING
A multiplication method and a modular multiplier are provided. The multiplication method includes transforming a redundantform multiplier by adding a recoding constant to the multiplier,...


US20120323982 
METHOD AND STRUCTURE FOR PROVABLY FAIR RANDOM NUMBER GENERATOR
A random number generator includes a fairness checker and correction module that ensures that a complete random sequence within a predetermined period of time will be output by the random number...


US20110047199 
CORRELATION APPARATUS AND METHOD FOR ACQUIRING ROBUST SYNCHRONIZATION
Provided is a correlation apparatus and method for acquiring a robust synchronization. The correlation method may include: calculating a received symbol phase difference with respect to a received...


US20110289128 
Method of performing discrete cosine transform
The present invention provides method and apparatus of a fast DCT implementation. DCT calculation is combined with quantization scales by a procedure of preprocessing. During DCT coefficient...
