Matches 1 - 34 out of 34


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US20120047194 COMPARING DATA SAMPLES REPRESENTED BY CHARACTERISTIC FUNCTIONS  
According to certain embodiments, a first characteristic function representing a first set of samples and a second characteristic function representing a second set of samples are generated. The...
US20070244960 Configurable IC's with large carry chains  
Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each...
US20070244958 Configurable IC's with carry bypass circuitry  
Some embodiments provide a configurable IC that includes several configurable logic circuits. The logic circuits include several sets of associated configurable logic circuits, each set for...
US20070244959 Configurable IC's with dual carry chains  
Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each of...
US20070244957 Configurable IC's with configurable logic circuits that perform adder and/or subtractor operations  
Some embodiments provide a configurable IC that includes a set of configurable logic circuits each for configurably performing a set of functions. A particular configurable logic circuit receives...
US20110153709 DELAY OPTIMAL COMPRESSOR TREE SYNTHESIS FOR LUT-BASED FPGAS  
A compressor tree synthesis algorithm, named DOCT, which guarantees the delay optimal implementation in LUT-based FPGAs. Given a targeted K-input LUT architecture, DOCT firstly derives a finite...
US20120134325 BRANCH METRICS CALCULATION FOR MULTIPLE COMMUNICATIONS STANDARDS  
A method for branch metric calculation in a plurality of communications standards is disclosed. The method generally includes steps (A) to (C). Step (A) may calculate a plurality of sum values by...
US20080046498 Carry-Select Adder Structure and Method to Generate Orthogonal Signal Levels  
A Carry-Select Adder structure comprising a carry generation network and a multiplexer to select a particular pre-calculatad sum of a bit-group via orthogonal signal levels of a Hot-Carry signal...
US20060149805 Implementation of digital signal processing functions using maximal efficiency and minimal energy dissipation  
Herein described is a method and system of implementing integrated circuit logic modules that provide maximum efficiency and minimum energy dissipation. In a representative embodiment, a method of...
US20130311534 DEVICE WITH LOGIC CIRCUITRY SUPPORTING QUATERNARY ADDITION  
A lookup table structure having multiple lookup tables is configured to include a quaternary adder. In particular examples, an adaptive logic module (ALM) including a fracturable lookup table...
US20060206557 Arithmetic logic unit circuit  
An Arithmetic Logic Unit that includes first multiplexers coupled to a first adder, the first multiplexers controlled by a first opcode register; second multiplexers receiving input from the first...
US20090313315 N-digit subtraction unit, N-digit subtraction module, N-digit addition unit and N-digit addition module  
Provided are N-digit addition and subtraction units and N-digit addition and subtraction modules in which borrowing and carrying are not propagated in modules having basic digits. In the units and...
US20070271326 Technical Solution to Written Calculations Engineering of the Digital Engineering Method for Hybrid Numeral Carry System and Carry Line  
The present invention relates to the digital engineering method and the field of written calculation engineering, and it puts forward a new digital engineering method which could remarkably...
US20100146031 Direct Decimal Number Tripling in Binary Coded Adders  
The digital propagate, digit generate, sum+0, and sum+1 terms used in typical carry-propagate adders are generated directly off the multiplicand. During the direct generation, the logic takes into...
US20070180016 METHOD OF OPERAND WIDTH REDUCTION TO ENABLE USAGE OF NARROWER SATURATION ADDER  
An electronic computing circuit for implementing a method for reducing the bit width of two operands from a bit length N to a reduced bit length M, thus, M
US20070088774 Computer technical solution of mixed q-nary and carry line digital engineering method  
The present invention relates to the field of digital engineering method and processor, and puts forward a new digital engineering method, which could increase the operation speed. The mixed...
US20080177817 Inversion of alternate instruction and/or data bits in a computer  
A basic computer circuit (30) with alternate bits inverted. Two 18-bit registers (32, 34) are connected to ALU (36) to perform ripple-carry addition, wherein 1-high number representation is...
US20120311009 HYBRID ADDER USING DYNAMIC AND STATIC CIRCUITS  
A hybrid adder may include static partial sum circuits that operate to generate partial sums of operands, where each operand may be divided into groups that include multiple bits. A first subset...
US20060230095 Digital signal processing circuit having a pre-adder circuit  
A digital signal processing circuit having a pre-adder circuit includes; a first register block and a pre-adder circuit coupled to a multiplier circuit and to a set of multiplexers, where the set...
US20100057825 METHOD AND ELECTRONIC COMPUTING CIRCUIT FOR OPERAND WIDTH REDUCTION FOR A MODULO ADDER FOLLOWED BY SATURATION CONCURRENT MESSAGE PROCESSING  
A method for operand width reduction is described, wherein two N-bit input operands (A, B) of a bit width of N are processed and two M-bit output operands (A′, B′) of a reduced bit width of M are...
US20070027946 Method and system for high-speed floating-point operations and related computer program product  
A circuit for estimating propagated carries in an adder starting from operands that include actual addition inputs or at least one earlier carry, the circuit performs statistical circuit...
US20100164543 LOW-COMPLEXITY ELECTRONIC ADDER CIRCUITS AND METHODS OF FORMING THE SAME  
In various embodiments, an adder circuit includes a plurality of transistors, all of the transistors being of a single type selected from the group consisting of NMOS transistors and PMOS...
US20080288565 METHOD TO COMPARE AND SORT BINARY DATA  
A binary data comparison method is performed as follows. First, bits of a plurality of binary data are provided, and bit x of the plurality of binary data are summed, where x=n, n−1, . . . , 1 or...
US20120265797 MONTGOMERY MULTIPLICATION METHOD  
Disclosed is a method of modular multiplication of two L-bit numbers (X, Y), the result defined from XY+mM, where M is the modulo, of L bits, and m is a number of L bits found and is divisible by...
US20090248781 METHOD AND DEVICE FOR DYNAMICALLY VERIFYING A PROCESSOR ARCHITECTURE  
A method and device may be useful for dynamically verifying a processor architecture at runtime. The checker may more efficiently and cheaply verify at least some of the functionality provided by...
US20060230096 Digital signal processing circuit having an adder circuit with carry-outs  
An integrated circuit having a digital signal processing (DSP) circuit is disclosed. The DSP circuit includes: a plurality of multiplexers receiving a first set, second set, and third set of input...
US20120124120 ADDER  
According to an embodiment, an adder includes first and second wave computing units and a threshold wave computing unit. Each of the first and second wave computing units includes a pair of first...
US20110106869 Method of Addition with Multiple Operands, Corresponding Adder and Computer Program Product  
A method is provided for adding binary numbers, each of N bits, based on an accumulation mechanism which, for each iteration of index i+1 with I>0, generates an estimation signal Ui+1 on N bits...
US20100312945 INTELLIGENT MEMORY BANKS FOR STORING VECTORS  
An intelligent memory bank for use with interleaved memories storing plural vectors comprises setup apparatus (96) receives an initial address (B+C+V+NMSK) and spacing data (D) for each vector....
US20100262639 DIGITAL DATA PROCESSOR  
A digital data processor which receives an N-bit input signal from a data source and converts the N-bit input signal into an M-bit output signal, the M-bit being larger than the N-bit. The digital...
US20100198895 Digital Signal Processor Having Instruction Set With A Logarithm Function Using Reduced Look-Up Table  
A digital signal processor is provided having an instruction set with a logarithm function that uses a reduced look-up table. The disclosed digital signal processor evaluates a logarithm function...
US20160313975 MULTI-BIT FULL ADDER BASED ON RESISTIVE-SWITCHING DEVICES AND OPERATION METHODS THEREOF  
The present disclosure discloses a full adder based on resistive-switching devices and an operation method thereof. A multi-bit full adder circuit is constituted by using a cross-bar array of...
US20140214913 ADDER CAPABLE OF SUPPORTING ADDITION AND SUBTRACTION OF UP TO N-BIT DATA AND METHOD OF SUPPORTING ADDITION AND SUBTRACTION OF A PLURALITY OF DATA TYPE USING THE ADDER  
An adder for supporting multiple data types by controlling a carry propagation is provided. The adder includes a plurality of first addition areas configured to receive pieces of incoming operand...
US20120036172 Expanded Scope Incrementor  
An incrementor circuit and method for incrementing is provided that computes an output data word by increasing an input data word magnitude by one of several integer values. The incrementor...

Matches 1 - 34 out of 34