Matches 1 - 5 out of 5


Match Document Document Title
US20130080491 FAST CONDITION CODE GENERATION FOR ARITHMETIC LOGIC UNIT  
In one embodiment, a microprocessor includes fetch logic for retrieving an instruction, decode logic configured to identify a plurality of operands and a multiply operation specified in the...
US20090132629 Method for Providing a Decimal Multiply Algorithm Using a Double Adder  
A method for performing decimal multiplication including storing a multiplier and a multiplicand in operand registers, the multiplier including one or more digits. A running sum is stored in a...
US20070266072 Method and apparatus for decimal number multiplication using hardware for binary number operations  
According to embodiments of the subject matter disclosed in this application, decimal floating-point multiplications and/or decimal fixed-point multiplications may be implemented using existing...
US20120089658 MODULO OPERATION METHOD AND APPARATUS FOR SAME  
The present invention provides a modulo operation method. The modulo operation method, in a case where the square of a divisor N is greater than or equal to a dividend C, includes: determining the...
US20120117136 Data verification algorithm for RF receivers  
Sending a set of two data, having actual data and calculated data by using the actual data, to a communication device using RF signal works as a virtual check sum function.
Matches 1 - 5 out of 5