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US20130346462 INTERCONNECTED ARITHMETIC LOGIC UNITS  
An arithmetic logic stage in a graphics pipeline includes a number of arithmetic logic units (ALUs). The ALUs each include, for example, a multiplier and an adder. The ALUs are interconnected by...
US20140280427 METHOD AND SYSTEM FOR DECOMPOSING SINGLE-QUBIT QUANTUM CIRCUITS INTO A DISCRETE BASIS  
A target quantum circuit expressed in a first quantum gate basis may be transformed into a corresponding quantum circuit expressed in a second quantum gate basis, which may be a universal set of...
US20150088947 MULTIPLY ADD FUNCTIONAL UNIT CAPABLE OF EXECUTING SCALE, ROUND, GETEXP, ROUND, GETMANT, REDUCE, RANGE AND CLASS INSTRUCTIONS  
A method is described that involves executing a first instruction with a functional unit. The first instruction is a multiply-add instruction. The method further includes executing a second...
US20110055308 Method And System For Multi-Precision Computation  
Systems and methods for multi-precision computation are disclosed. One embodiment of the present invention includes a plurality of multiply-add units (MADDs) configured to perform one or more...
US20120011187 PARALLEL REDUNDANT DECIMAL FUSED-MULTIPLY-ADD CIRCUIT  
A circuit for performing a floating-point fused-multiply-add (FMA) calculation of a×b±c. The circuit includes (i) a partial product generation module having (a) a multiples generator unit...
US20110029589 LOW POWER FIR FILTER IN MULTI-MAC ARCHITECTURE  
Embodiments of the invention are directed to system and method that enable relatively low power dissipation by scheduling operations of multiply accumulators chain of two or more multiply...
US20140101220 COMPOSITE FINITE FIELD MULTIPLIER  
A composite finite field multiplier is disclosed. The multiplier includes a controller, an input port, an output port, a GF((2n)2) multiplier, a GF(2n) standard basis multiplier, and a GF(2n)...
US20110185000 Method for carry estimation of reduced-width multipliers  
A low-error reduced-width multiplier is provided by the present invention. The multiplier can dynamically compensate the truncation error. The compensation value is derived by the dependencies...
US20140095568 Fused Multiply-Adder with Booth-Encoding  
A fused multiply-adder is disclosed. The fused multiply-adder includes a Booth encoder, a fraction multiplier, a carry corrector, and an adder. The Booth encoder initially encodes a first operand....
US20130332501 Fused Multiply-Adder with Booth-Encoding  
A fused multiply-adder is disclosed. The fused multiply-adder includes a Booth encoder, a fraction multiplier, a carry corrector, and an adder. The Booth encoder initially encodes a first operand....
US20140095570 APPARATUS AND METHOD FOR CALCULATING INTERNAL STATE FOR ARTIFICIAL EMOTION  
An apparatus and method for calculating an internal state for artificial emotions are disclosed, of which the method comprises multiplying an input value obtained from a sensor with a first...
US20110055303 Function Generator  
One embodiment relates to a method for generating a periodic function in response to an argument in a digital signal processing system, where the periodic function can be represented as functions...
US20140222883 MATH CIRCUIT FOR ESTIMATING A TRANSCENDENTAL FUNCTION  
A math circuit for computing an estimate of a transcendental function is described. A lookup table storage circuit has stored therein several groups of binary values, where each group of values...
US20090177447 Method for Estimating Software Development Effort  
A method for estimating software development effort comprises the steps of: generating a database containing a plurality of source softwares; calculating the Grey relational coefficients between...
US20150081753 TECHNIQUE FOR PERFORMING ARBITRARY WIDTH INTEGER ARITHMETIC OPERATIONS USING FIXED WIDTH ELEMENTS  
One embodiment of the present invention includes a method for performing arithmetic operations on arbitrary width integers using fixed width elements. The method includes receiving a plurality of...
US20110320512 Decimal Floating Point Mechanism and Process of Multiplication without Resultant Leading Zero Detection  
A decimal multiplication mechanism for fixed and floating point computation in a computer having a coefficient mechanism without resulting leading zero detection (LZD) and process which assumes...
US20090313236 SEARCHING, SORTING, AND DISPLAYING VIDEO CLIPS AND SOUND FILES BY RELEVANCE  
A documents database has a plurality of documents, including but not limited to text files, video clips and sound files. Each document is associated with at least one category of a plurality of...
US20140082036 PERFORMING A DIVISION OPERATION USING A SPLIT DIVISION CIRCUIT  
The disclosed embodiments disclose techniques for using a split division circuit that includes a first divider that is optimized for a first range of divisor values and a second divider that is...
US20080140753 Multiplier  
An electronically implemented method includes multiplying a number A, and a number B, where A is composed of segments ai and B is composed of segments bj where i and j are integers greater than 1....
US20060277242 Combining circuitry  
A combining circuit and method combines a plurality of terms in a multiplier circuit. The combining circuit includes a first circuit, arranged to receive a first set of the plurality of terms and...
US20080098057 Multiplication Apparatus  
There is provided a multiplication apparatus for generating a product of a multiplicand and a multiplier, each of which is a fixed point number represented in two's complement. The multiplication...
US20150095394 MATH PROCESSING BY DETECTION OF ELEMENTARY VALUED OPERANDS  
One embodiment of the present invention includes a method for simplifying arithmetic operations by detecting operands with elementary values such as zero or 1.0. Computer and graphics processing...
US20050138100 Product-sum operation circuit and method  
A product-sum operation circuit includes a sorting block (4) which outputs a plurality of operand values x1, x2, . . . xi in descending or ascending order of magnitude, and an operation unit (1)...
US20090248779 Processor which Implements Fused and Unfused Multiply-Add Instructions in a Pipelined Manner  
Implementing an unfused multiply-add instruction within a fused multiply-add pipeline. The system may include an aligner having an input for receiving an addition term, a multiplier tree having...
US20140379774 SYSTEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR PERFORMING MATHEMATICAL OPERATIONS  
The system has first, second, third, and fourth subsystems. Each subsystem has first and second multipliers coupled, respectively, to first and second adders. Each multiplier has two inputs. The...
US20140289293 LARGE MULTIPLIER FOR PROGRAMMABLE LOGIC DEVICE  
A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier...
US20110161389 LARGE MULTIPLIER FOR PROGRAMMABLE LOGIC DEVICE  
A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier...
US20090150471 RECONFIGURABLE ARITHMETIC UNIT AND HIGH-EFFICIENCY PROCESSOR HAVING THE SAME  
Provided are a reconfigurable arithmetic unit and a processor having the same. The reconfigurable arithmetic unit can perform an addition operation or a multiplication operation according to an...
US20080195685 Multi-format multiplier unit  
Multiplication engines and multiplication methods are provided. A multiplication engine for a digital processor includes a first multiplier to generate unequally weighted partial products from...
US20090287757 Leading Zero Estimation Modification for Unfused Rounding Catastrophic Cancellation  
Modifying a leading zero estimation during an unfused multiply add operation of (A*B)+C. A plurality of terms x and y may be received, and each may be based on truncated terms s and t (e.g., in...
US20110264719 HIGH RADIX DIGITAL MULTIPLIER  
The present invention relates to power and hardware efficient digital multipliers configured to multiply an N-bit multiplicand with an M-bit multiplier. The digital multipliers comprise efficient...
US20130262549 ARITHMETIC CIRCUIT AND ARITHMETIC METHOD  
An arithmetic circuit includes a circuit to output n-th multiples of a multiplicand, a circuit to output an XOR operation result that is a result of performing an exclusive logical sum operation...
US20080071847 Method for Transforming Data by Look-Up Table  
Provided is a method for transforming data using a look-up table. The method includes the steps of: (a) mapping preprocessed input binary data to a constellation diagram divided into four...
US20100023569 METHOD FOR COMPUTERIZED ARITHMETIC OPERATIONS  
A method of computing arithmetic operations more efficiently than the conventional Arithmetic Logic Unit (ALU) is disclosed. By encoding both operands from Binary Coded Decimal (BCD) codes (0000,...
US20060173946 Common shift-amount calculation for binary and hex floating point  
A method and system for performing a binary mode and hexadecimal mode Multiply-Add floating point operation in a floating point arithmetic unit according to a formula A*C+B, wherein A, B and C...
US20130346461 APPARATUS FOR CALCULATING A RESULT OF A SCALAR MULTIPLICATION  
An apparatus for calculating a result of a scalar multiplication of a reference number with a reference point on an elliptic curve comprises a point selector and a processor. The point selector is...
US20090070399 ARITHMETIC PROCESSING SYSTEM AND METHOD THEREOF  
An arithmetic processing system processes a sensing signal and a first approximate offset signal to obtain a second approximate offset signal. The system includes a first arithmetic processor and...
US20050165876 Multiple-word multiplication-accumulation circuit and Montgomery modular multiplication-accumulation circuit  
A multiple-word multiplication-accumulation circuit suitable for use with a single-port memory. The circuit is composed of a multiplication-accumulation (MAC) operator and surrounding registers....
US20070061392 Fused multiply add split for multiple precision arithmetic  
An apparatus and method for performing floating-point operations, particularly a fused multiply add operation. The apparatus includes a arithmetic logic unit adapted to produce both a high-order...
US20090292756 Large-factor multiplication in an array of processors  
A processor to calculate a product-component having fewer digits than an entire product of a multiplication of a multiplicand and a multiplier. A memory holds at least one multiplicand-component...
US20090030963 MULTIPLICATION CIRCUIT, DIGITAL FILTER, SIGNAL PROCESSING DEVICE, SYNTHESIS DEVICE, SYNTHESIS PROGRAM, AND SYNTHESIS PROGRAM RECORDING MEDIUM  
The conventional two's complement multiplier which is constituted by a Booth encoder, a partial production generation circuit, and an adder has a problem that the circuit scale would be increased...
US20120078992 FUNCTIONAL UNIT FOR VECTOR INTEGER MULTIPLY ADD INSTRUCTION  
A vector functional unit implemented on a semiconductor chip to perform vector operations of dimension N is described. The vector functional unit includes N functional units. Each of the N...
US20090077154 Microprocessor  
Provided is a microprocessor including a complex-MAC unit that operates in response to a complex-MAC instruction. The complex-MAC unit receives first and second complex data (each having 2m-bit...
US20080114826 Single Precision Vector Dot Product with "Word" Vector Write Mask  
The present invention is generally related to the field of image processing, and more specifically to an instruction set for processing images. Vector processing may involve performing a plurality...
US20070185953 Dual Mode Floating Point Multiply Accumulate Unit  
Included are embodiments of a Multiply-Accumulate Unit to process multiple format floating point operands. For short format operands, embodiments of the Multiply Accumulate Unit are configured to...
US20080256162 X87 FUSED MULTIPLY-ADD INSTRUCTION  
An x87 fused multiply-add (FMA) instruction in the instruction set of an x86 architecture microprocessor is disclosed. The FMA instruction implicitly specifies the two factor operands as the top...
US20070106720 Reconfigurable signal processor architecture using multiple complex multiply-accumulate units  
A reconfigurable digital signal processor (DSP) comprises: a reconfigurable data path comprising a plurality of reconfigurable multiply-accumulate (MAC) units; and a programmable finite state...
US20100306301 ARITHMETIC PROCESSING UNIT THAT PERFORMS MULTIPLY AND MULTIPLY-ADD OPERATIONS WITH SATURATION AND METHOD THEREFOR  
Sum and carry signals are formed representing a product of a first and a second operand. A bias signal is formed having a value determined by a sign of a product of the first and the second...
US20100250640 SYSTOLIC ARRAY AND CALCULATION METHOD  
A linear systolic array is added to the lower side of a trapezoid systolic array created by combining a triangular systolic array and a square systolic array. In order to make the connection among...
US20060253519 Processor core and multiplier that support a multiply and difference operation by inverting sign bits in booth recoding  
The present invention provides processing systems, apparatuses, and methods that support both general processing processor (GPP) and digital signal processor (DSP) features, such as vector and...

Matches 1 - 50 out of 81 1 2 >