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US20130091189 
Single datapath floating point implementation of RCP, SQRT, EXP and LOG functions and a low latency RCP based on the same techniques
Methods and apparatus is provided for computing mathematical functions comprising a single pipeline for performing a polynomial approximation (e.g. a quadratic polynomial approximation, or the... 

US20130346462 
INTERCONNECTED ARITHMETIC LOGIC UNITS
An arithmetic logic stage in a graphics pipeline includes a number of arithmetic logic units (ALUs). The ALUs each include, for example, a multiplier and an adder. The ALUs are interconnected by... 

US20140285493 
METHOD AND APPARATUS TO DISPLAY THE TIME OF DAY AS A MATHEMATICAL EXPRESSION
A method of showing the time of day by displaying a mathematical expression. A display capable of showing numbers, letters, and other characters is used. A plurality of numbers in conjunction with... 

US20100191793 
Symbolic Computation Using TreeStructured Mathematical Expressions
A method for performing symbolic computations on a mathematical expression. The mathematical expression may be converted to a tree structure having one or more parent nodes and one or more child... 

US20120237025 
DEVICE AND METHOD FOR DETERMINING AN INVERSE OF A VALUE RELATED TO A MODULUS
A device for determining an inverse of an initial value related to a modulus, comprising a unit configured to process an iterative algorithm in a plurality of iterations, wherein an iteration... 

US20060015552 
Analog square root calculating circuit for a sampled data system and method
A square root calculating circuit is provided for an analog sampled data system. The square root calculating circuit includes a summing integrator circuit and a multiplier circuit. The summing... 

US20140222883 
MATH CIRCUIT FOR ESTIMATING A TRANSCENDENTAL FUNCTION
A math circuit for computing an estimate of a transcendental function is described. A lookup table storage circuit has stored therein several groups of binary values, where each group of values... 

US20140046991 
ARITHMETIC LOGIC UNIT FOR USE WITHIN A FLIGHT CONTROL SYSTEM
An arithmetic logic unit (ALU) for use within a flight control system is provided. The ALU comprises a first register configured to receive a first operand, a second register configured to receive... 

US20070016635 
Inversion calculations
An Elliptic Curve Cryptography inversion technique utilises operating on the MSW of four auxiliary variables U, V, R and S with specified invariences. 

US20150220307 
OPERATION BASED ON TWO OPERANDS
A method for performing an operation based on at least two operands is proposed, in which steps of the operation are performed in timerandomized fashion. In addition, an apparatus, a computer... 

US20110231467 
MONTGOMERY MULTIPLIER HAVING EFFICIENT HARDWARE STRUCTURE
A radix2k Montgomery multiplier including an input coefficient generation unit to receive a multiplier, a multiplicand, a modulus, a sum and a previous sum, to generate and to output a partial... 

US20070083584 
INTEGRATED MULTIPLY AND DIVIDE CIRCUIT
The principles of the present invention relate to a multiply and divide circuit configured to interactively multiply and/or divide. The circuit may handle signed and unsigned values. The circuit... 

US20150095394 
MATH PROCESSING BY DETECTION OF ELEMENTARY VALUED OPERANDS
One embodiment of the present invention includes a method for simplifying arithmetic operations by detecting operands with elementary values such as zero or 1.0. Computer and graphics processing... 

US20130159371 
Arithmetic Logic Unit Architecture
Embodiments of the present invention include an apparatus, method, and system for acoustic modeling. In an embodiment, an arithmetic logic unit for computing a onedimensional score between a... 

US20050144210 
Programmable logic device with dynamic DSP architecture
Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each slice includes a mode port that receives... 

US20070214204 
Negative two's complement numbering system
The present invention provides a solution to the shortcomings of the traditional two's complement system that is commonly utilized in modern computing systems and digital signal processors. The... 

US20070174378 
Computation of logarithmic and exponential functions
Efficiency of computation of logarithmic and exponential functions may be improved using multiplication by precomputed coefficients to obtain intermediate products. 

US20070260662 
ControlledPrecision Iterative Arithmetic Logic Unit
A controlledprecision Iterative Arithmetic Logic Unit (IALU) included in a processor produces subprecision results, i.e. results having a bit precision less than full precision. In one... 

US20070233767 
Rotator/shifter arrangement
Embodiments related to rotator/shifter arrangements are presented herein. 

US20140229517 
Automatic Computer Program Obfuscation System
A computer program obfuscating system including a processor to provide a computer program including at least one computer program variable, and add an opaque predicate to the computer program to... 

US20140067893 
Squaring Circuit
Methods, apparatuses, and computer program products for squaring an operand include identifying a fixedpoint value with a fixed word size and a substring size for substrings of the fixedpoint... 

US20060047738 
Decimal rounding mode which preserves data information for further rounding to less precision
A method of processing data employs a new rounding mode called “round for reround” on the original arithmetic instruction in the hardware precision, and then 2) invoking an instruction which... 

US20070250559 
Broadband transfer function synthesis using orthonormal rational bases
In order to generate a broadband transfer function of complex characteristics of a linear timeinvariant (LTI) system, data characterising properties of the system are acquired. A set of poles in... 

US20130290392 
INSTRUCTION AND LOGIC FOR PERFORMING A DOTPRODUCT OPERATION
Method, apparatus, and program means for performing a dotproduct operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first... 

US20070198625 
Conditional negating booth multiplier
An angle rotator performs angle rotation of an input complex signal in the complex plane according to an angle θ. The angle rotator includes a coarse stage rotation and a fine stage rotation. The... 

US20060269054 
Extending the range of computational fields of intergers
An extension of the serial/parallel Montgomery modular multiplication method with simultaneous reduction as previously implemented by the applicants, adapted innovatively to perform both in the... 

US20050223051 
System for building structured spreadsheets using nested named rectangular blocks of cells to form a hierarchy where cells can be uniquely referenced using non unique names
This system is a way of building structured spreadsheets using named nested rectangular block of cells to form a hierarchy. This system allows cells to be referenced by non unique names by using... 

US20060190516 
Digital signal processing element having an arithmetic logic unit
A digital signal processing circuit including: a multiplier circuit; a plurality of. multiplexers coupled to the multiplier circuit and controlled by a first opcode; and an arithmetic logic unit... 

US20070260663 
Cyclic segmented prefix circuits for mesh networks
Parallel prefix circuits for computing a cyclic segmented prefix operation with a mesh topology are disclosed. In one embodiment of the present invention, the elements (prefix nodes) of the mesh... 

US20060129623 
Division and square root arithmetic unit
A division and square root arithmetic unit carries out a division operation of a higher radix and a square root extraction operation of a lower radix. A certain bit number (determined on the basis... 

US20070043801 
Performing rounding in an arithmetic operation
An arithmetic unit comprising: an encoding circuit arranged to receive first and second operands each having a bit length of m bits and to generate therefrom a number n of partial products of... 

US20070198624 
Using a Document Model to Create and Maintain Dynamic Mathematic Representations Through Problem Spaces
A device operable to maintain a document comprising a processor, a first problem space including a first variable having a first value, and a second problem space including a second variable... 

US20050131979 
Apparatus for calculating absolute difference value, and motion estimation apparatus and motion picture encoding apparatus which use the apparatus for calculating the absolute difference value
An apparatus calculates an absolute difference value, which facilitates an efficient structure of an SAD calculating unit having a treelike structure, and a motion estimation apparatus and a... 

US20140214912 
PERFORMING BATCHES OF SELECTIVE ASSIGNMENTS IN A VECTOR FRIENDLY MANNER
Embodiments of the invention relate to processing queries. A query operation to be performed on a table of data is translated into a series of bit level logical operations using expansion and/or... 

US20140244703 
SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING LARGE INTEGER OPERATIONS ON A GRAPHICS PROCESSING UNIT
A system, method, and computer program product for generating executable code for performing large integer operations on a parallel processing unit is disclosed. The method includes the steps of... 

US20080281896 
INDUSTRIAL CONTROLLER
A first arithmetic operator (11) includes a first modular arithmetic coding encoder (11b) for encoding a numeric data transmitted by a command from a central controller (31) into a modular... 

US20060075011 
System and method for optimizing polynomial expressions in a processing environment
A method for optimizing polynomial expressions is provided that includes generating kernels in order to form a kernel and cokernel matrix and generating a cube literal matrix, which includes a... 

US20080154996 
DATAPIPE SYNCHRONIZATION DEVICE
A programmable element for data processing comprises a crosspoint switch (318), a mathematical operation module (320), and a plurality of data hold modules (604,606). Each of the data hold modules... 

US20060230092 
Architectural floorplan for a digital signal processing circuit
A physical floorplan for a digital signal processing (DSP) block including; an interconnect column having a plurality of programmable interconnect elements; a first DSP element having a plurality... 

US20150088952 
ARITHMETIC PROCESSING DEVICE
An arithmetic processing device includes: a reception unit for receiving information including a numerical value and an operator; a generation unit generating arithmetic information regarding an... 

US20050010630 
Method and apparatus for determining a remainder in a polynomial ring
The present invention relates to a method and an apparatus for determining a remainder in a polynomial ring. The apparatus for determining a remainder in a polynomial ring according to the... 

US20070192395 
METHOD FOR DATABASEDRIVEN ESTIMATE OF AN OUTPUT QUANTITY IN A KDIMENSIONAL VALUE RANGE
Method for the databasedriven estimate of an output quantity in a kdimensional value range. The method includes determining a location probability range Ri for a kdimensional output quantity... 

US20070239816 
Formation Process for Logical and Control Functions in Information Processing and Control Systems
The invention concerns generally radio electronics in particular it relates to computer facilities and can be used in information processing and control systems. The process includes an operation... 

US20070260664 
Computation of a multiplication operation with an electronic circuit and method
A computing method and circuit for computing a modular operation with at least one operand having a binary representation. Iteratively for each bit of this operand, doubling the value of an... 

US20060253517 
Using binary array representations of sequences to eliminate redundant patterns in discovered patterns of symbols
The present invention relates to computerimplemented methods for finding patterns in patterns in a set of ksequences of symbols (where k≧2) and to a computer readable medium having instructions... 

US20070168410 
TRANSFORMS WITH COMMON FACTORS
Techniques for efficiently performing transforms on data are described. In one design, an apparatus performs multiplication of a first group of at least one data value with a first group of at... 

US20070239817 
Rounding computing method and computing device therefor
A computing device has a rounding processor that inputs therein a set of plural (K) input data IN1 through INK comprising z bits. The rounding processor selects an ensured bit field depending upon... 

US20080126465 
Calendarbased Financial Calculator
A computer operated, calendarbased financial calculator comprises a computer display, calendar calculating software, and a calculation engine, so as to provide a visual presentation of any... 

US20080059551 
Device and Method for Composing Codes
Configurable vector processors can be equipped with code generators, so that they are capable of handling different standards and codes. Furthermore, they can be arranged to provide support for... 

US20120254275 
RELIABLE AND EFFICIENT COMPUTATION OF MODAL INTERVAL ARITHMETIC OPERATIONS
A computer executable method of performing a modal interval operation, and system for performing same is provided. The method includes providing representations of first and second modal interval... 