Match

Document 
Document Title 

US20120102081 
LOWLATENCY ARCTANGENT CALCULATION STRUCTURE AND CALCULATION METHOD THEREOF
The present invention provides a lowlatency arctangent calculation structure and a calculation method thereof. The arctangent calculation structure comprises two lookup tables, a subtractor, a... 

US20150088947 
MULTIPLY ADD FUNCTIONAL UNIT CAPABLE OF EXECUTING SCALE, ROUND, GETEXP, ROUND, GETMANT, REDUCE, RANGE AND CLASS INSTRUCTIONS
A method is described that involves executing a first instruction with a functional unit. The first instruction is a multiplyadd instruction. The method further includes executing a second... 

US20130218938 
FLOATINGPOINT ADDER WITH OPERAND SHIFTING BASED ON A PREDICTED EXPONENT DIFFERENCE
Provided are a floatingpoint adder and methods for implementing a floatingpoint adder with operand shifting based on a predicted exponent difference when performing an effective subtraction on... 

US20110208794 
COMPUTING HALF INSTRUCTIONS OF FLOATING POINT NUMBERS WITHOUT EARLY ADJUSTMENT OF THE SOURCE OPERANDS
Apparatus and methods are disclosed for a floating point adder having halfadder capability that does not have the overhead of determining halfadder conditions prior to starting the SED, LED, and... 

US20100312812 
Decimal FloatingPoint Adder with Leading Zero Anticipation
A decimal floatingpoint (DFP) adder includes a decimal leadingzero anticipator (LZA). The DFP adder receives DFP operands. Each operand includes a significand, an exponent, a sign bit and a... 

US20110302229 
CALCULATING LARGE PRECISION COMMON LOGARITHMS
Techniques are disclosed for calculating large precision common logarithms. A common logarithm may be calculated using addition and/or subtraction of known logarithm values. Embodiments of the... 

US20130151576 
APPARATUS AND METHOD FOR ROUNDING A FLOATINGPOINT VALUE TO AN INTEGRAL FLOATINGPOINT VALUE
Processing circuitry is provided to perform an operation FRINT for rounding a floatingpoint value to an integral floatingpoint value. Control circuitry controls the processing circuitry to... 

US20140192977 
MUTIPLICATION METHOD AND MODULAR MULTIPLIER USING REDUNDANT FORM RECODING
A multiplication method and a modular multiplier are provided. The multiplication method includes transforming a redundantform multiplier by adding a recoding constant to the multiplier,... 

US20130179664 
DIVISION UNIT WITH MULTIPLE DIVIDE ENGINES
Techniques are disclosed relating to integrated circuits that include hardware support for divide and/or square root operations. In one embodiment, an integrated circuit is disclosed that includes... 

US20150067010 
FLOATINGPOINT ADDER CIRCUITRY
An integrated circuit is provided that performs floatingpoint addition or subtraction operations involving at least three floatingpoint numbers. The floatingpoint numbers are preprocessed by... 

US20120143934 
MECHANISM FOR CARRYLESS MULTIPLICATION THAT EMPLOYS BOOTH ENCODING
An apparatus having operand registers, an opcode dectector, a carryless preformat unit, a compressor, a left shifter, and exclusiveOR logic. The operand registers receive operands for a carryless... 

US20110314073 
METHODS FOR EFFICIENT STATE TRANSITION MATRIX BASED LFSR COMPUTATIONS
A method for efficient state transition matrix based LFSR computations are disclosed. A polynomial associated with a linear feedback shift register is defined. This polynomial is used to generate... 

US20110231460 
APPARATUS AND METHOD FOR FLOATINGPOINT FUSED MULTIPLY ADD
A fused multiply add (FMA) unit includes an alignment counter configured to calculate an alignment shift count, an aligner configured to align an addend input based on the alignment shift count... 

US20150199173 
MULTIPLY ADDER
A floating point multiply add circuit 24 includes a multiplier 26 and an adder 28. The input operands A, B and C together with the result value all have a normal exponent value range, such as a... 

US20130103730 
Microprocessor Shifter Circuits Utilizing Butterfly and Inverse Butterfly Routing Circuits, and Control Circuits Therefor
Microprocessor shifter circuits utilizing butterfly and inverse butterfly circuits, and control circuits therefor, are provided. The same shifter circuits can also perform complex bit... 

US20140188963 
EFFICIENT CORRECTION OF NORMALIZER SHIFT AMOUNT ERRORS IN FUSED MULTIPLY ADD OPERATIONS
A method for correcting a shift error in a fused multiply add operation. The method comprises adjusting a normalized floatingpoint number before performing a shift error correction to produce an... 

US20140164457 
EXTENSIBLE ITERATIVE MULTIPLIER
An extensible iterative multiplier design is provided. Embodiments provide cascaded 8bit multipliers for simplifying the performance of multibyte multiplications. Booth encoding is performed in... 

US20130159367 
Implementation of Negation in a Multiplication Operation Without PostIncrementation
A multiplier circuit for generating a product of at least first and second multiplicands includes encoding circuitry comprising a plurality of encoders. Each of the encoders is operative to... 

US20140059096 
DIVIDING DEVICE AND DIVIDING METHOD
A dividing device includes: shifting circuits which leftshift the mantissa parts of the dividend and the divisor by a first and a second count values; a digit number arithmetic circuit which... 

US20120197954 
FLOATING POINT MULTIPLIER CIRCUIT WITH OPTIMIZED ROUNDING CALCULATION
An optimized floating point multiplier rounding circuit that minimizes the increase of the critical timing path of the calculation. The values of the temporary mantissa required to make the... 

US20110106868 
Floating point multiplier with partial product shifting circuitry for result alignment
A floating point multiplier includes a data path in which a plurality of partial products are calculated and then reduced to a first partial product and a second partial product. Shift amount... 

US20100299378 
SORTABLE FLOATING POINT NUMBERS
The invention comprises methods for manipulating floating point numbers on a microprocessor where the numbers are sortable. That is, the numbers obey lexicographical ordering. Hence, the numbers... 

US20120215939 
BINARYSHIFT OPERATIONS SUCH AS FOR HEADER COMPRESSION IN PACKETBASED COMMUNICATIONS
In one embodiment of a headercompression method, a timestamp value is divided by a stride value using a plurality of binaryshift operations corresponding to a Taylor expansion series of the... 

US20140082037 
PERFORMING QUOTIENT SELECTION FOR A CARRYSAVE DIVISION OPERATION
The disclosed embodiments disclose techniques for performing quotient selection in an iterative carrysave division operation that divides a dividend, R, by a divisor, D, to produce an... 

US20080270496 
COMPOSITION/DECOMPOSITION OF DECIMAL FLOATING POINT DATA
A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information... 

US20110320512 
Decimal Floating Point Mechanism and Process of Multiplication without Resultant Leading Zero Detection
A decimal multiplication mechanism for fixed and floating point computation in a computer having a coefficient mechanism without resulting leading zero detection (LZD) and process which assumes... 

US20140046991 
ARITHMETIC LOGIC UNIT FOR USE WITHIN A FLIGHT CONTROL SYSTEM
An arithmetic logic unit (ALU) for use within a flight control system is provided. The ALU comprises a first register configured to receive a first operand, a second register configured to receive... 

US20110022910 
ARITHMETIC LOGIC UNIT FOR USE WITHIN A FLIGHT CONTROL SYSTEM
An arithmetic logic unit (ALU) for use within a flight control system is provided. The ALU comprises a first register configured to receive a first operand, a second register configured to receive... 

US20140059097 
MULTIPLYING DEVICE AND MULTIPLYING METHOD
A multiplying device includes: a circuit which leftshifts a mantissa part of a floatingpoint number being a multiplicand by a shift amount; a circuit which calculates a digit number of the... 

US20080140744 
Dividers
The present invention relates to a divider for dividing a dividend by a divisor. The divider includes a subtractor for subtracting the divisor from the dividend to produce a result, storage space... 

US20130151578 
Performing Arithmetic Operations Using Both Large and Small Floating Point Values
Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are... 

US20130151577 
Performing Arithmetic Operations Using Both Large and Small Floating Point Values
Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are... 

US20130124590 
RECONFIGURABLE CYCLIC SHIFTER ARRANGEMENT
In one embodiment, a reconfigurable cyclic shifter arrangement has first and second reconfigurable cyclic shifters connected in series that are each selectively and independently configurable to... 

US20140082036 
PERFORMING A DIVISION OPERATION USING A SPLIT DIVISION CIRCUIT
The disclosed embodiments disclose techniques for using a split division circuit that includes a first divider that is optimized for a first range of divisor values and a second divider that is... 

US20140330878 
FAST COMPUTATION OF PRODUCTS BY DYADIC FRACTIONS WITH SIGNSYMMETRIC ROUNDING ERRORS
A product of an integer value and an irrational value may be determined by a signsymmetric algorithm. A process may determine possible algorithms that minimize metrics such as mean asymmetry,... 

US20090138534 
Microprocessor Shifter Circuits Utilizing Butterfly and Inverse Butterfly Routing Circuits, and Control Circuits Therefor
Microprocessor shifter circuits utilizing butterfly and inverse butterfly circuits, and control circuits therefor, are provided. The same shifter circuits can also perform complex bit... 

US20140032622 
Parameterized Digital Divider
A method of performing digital division includes rightshifting a divider to provide a temporary divider, subtracting the temporary divider from a temporary dividend to provide a difference,... 

US20100306292 
DSP Engine with Implicit Mixed Sign Operands
A processor may have at least one multiplier unit which can be controlled to operate in a signed, an unsigned, or a mixed sign mode; a multiplier unit mode decoder coupled with the multiplier unit... 

US20120117135 
METHOD FOR GENERATING A SEQUENCE IN A WIRELESS COMMUNICATION SYSTEM, AND APPARATUS FOR SAME
Disclosed is a method for generating a sequence and an apparatus for the same which can satisfy the number M′ of sequences sufficiently larger than a length N of a sequence required in a wireless... 

US20110264720 
CRYPTOGRAPHIC SYSTEM, METHOD AND MULTIPLIER
In general, in one aspect, the disclosure describes a multiplier that includes a set of multiple multipliers configured in parallel where the set of multiple multipliers have access to a first... 

US20080208939 
Decoder device and decoding method
A decoder having an element decoding unit generating external information for input data, including an exponent position determining unit, when the external information output from the element... 

US20100042665 
Subnormal Number Handling in Floating Point Adder Without Detection of Subnormal Numbers Before Exponent Subtraction
In an embodiment, a floating point unit (FPU) comprises an adder configured to add a first mantissa and a second mantissa and an operand adjust unit coupled to provide at least the first mantissa... 

US20140089362 
Modified FixedPoint Algorithm For Implementing Infrared Sensor Radiation Equation
A system including an integrated circuit chip also includes a microcontroller in the chip and an algorithm for execution by the microcontroller. The algorithm includes addition, subtraction, and... 

US20150199303 
Device and Method for Determining an Estimate of the Logarithm of an Input Variable
The disclosure relates to a device for determining an estimate of the logarithm of an input variable. The device has an approximation unit which is designed to use an approximation to determine... 

US20060031272 
Alignment shifter supporting multiple precisions
An apparatus, a method, and a computer program are provided for fully utilizing a double precision Floating Point (FP) alignment shifter. In conventional FP adders, and other FP computational... 

US20110219052 
DISCRETE FOURIER TRANSFORM IN AN INTEGRATED CIRCUIT DEVICE
Circuitry performing Discrete Fourier Transforms. The circuitry can be provided in a fixed logic device, or can be configured into a programmable integrated circuit device such as a programmable... 

US20120215823 
Apparatus and method for performing floating point addition
An apparatus and method are provided for performing an addition operation on operands A and B in order to produce a result R, the operands A and B and the result R being floating point values each... 

US20090089346 
Method For Performing A Division Operation In A System
A method for performing a division operation in a system includes a) determining an approximate quotient of a numerator value and a denominator value; b) determining an initial error of the... 

US20140289293 
LARGE MULTIPLIER FOR PROGRAMMABLE LOGIC DEVICE
A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier... 

US20110161389 
LARGE MULTIPLIER FOR PROGRAMMABLE LOGIC DEVICE
A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier... 