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US20120175585 CAGE NANOSTRUCTURES AND PREPARTION THEREOF  
A unique family of nanoparticles characterized by their nanometric size and cage-like shapes (hollow structures), capable of holding in their hollow cavity a variety of materials is disclosed herein.
US20090286383 TREATMENT OF WHISKERS  
A photo-curing or photosintering process is utilized to modify, reduce or eliminate whiskers or nanowires growing on a material surface.
US20140141537 PRODUCTION OF HIGH PRECIPITATE DENSITY WAFERS BY ACTIVATION OF INACTIVE OXYGEN PRECIPITATE NUCLEI  
Processes for the treatment of silicon wafers to form a high density non-uniform distribution of oxygen precipitate nuclei therein such that, upon being subjected to the heat treatment cycles of...
US20120034794 ENHANCING THE WIDTH OF POLYCRYSTALLINE GRAINS WITH MASK  
A system, method and masking arrangement are provided of enhancing the width of polycrystalline grains produced using sequential lateral solidification using a modified mask pattern is disclosed....
US20120083135 ASYMMETRIC RAPID THERMAL ANNEALING TO REDUCE PATTERN EFFECT  
Rapid thermal annealing methods and systems for annealing patterned substrates with minimal pattern effect on substrate temperature non-uniformity are provided. The rapid thermal annealing system...
US20130164948 METHODS FOR IMPROVING WAFER TEMPERATURE UNIFORMITY  
A method of improving temperature uniformity across a wafer or substrate is provided. The inventors have discovered that thermal radiation reflected from the showerhead injector affects the...
US20120248550 PLASMA DOPING TO REDUCE DIELECTRIC LOSS DURING REMOVAL OF DUMMY LAYERS IN A GATE STRUCTURE  
The embodiments of methods and structures disclosed herein provide mechanisms of performing doping an inter-level dielectric film, ILD0, surrounding the gate structures with a dopant to reduce its...
US20150194346 METHODS OF LOCALIZED HARDENING OF DICING CHANNEL  
Various embodiments include localized hardening of dicing channels in an integrated circuit (IC) wafer. In some embodiments, a method includes: applying localized heat to a metal interconnect in a...
US20090011614 RECONFIGURABLE SEMICONDUCTOR STRUCTURE PROCESSING USING MULTIPLE LASER BEAM SPOTS  
Methods and systems selectively irradiate structures on or within a semiconductor wafer using multiple laser beams. The structures may be laser-severable conductive links, and the purpose of the...
US20080299783 SYSTEMS AND METHODS FOR PROCESSING SEMICONDUCTOR STRUCTURES USING LASER PULSES LATERALLY DISTRIBUTED IN A SCANNING WINDOW  
Systems and methods process structures on or within a semiconductor substrate using a series of laser pulses. In one embodiment, a deflector is configured to selectively deflect the laser pulses...
US20140080322 Emissivity Profile Control for Thermal Uniformity  
A substrate for processing in a heating system is disclosed. The substrate includes a bottom portion for absorbing heat from a radiating heat source, the bottom portion having a first region...
US20050215077 Method for manufacturing a polycrystalline semiconductor film, apparatus thereof, and image display panel  
The generation of a projecting intensity distribution in an irradiation laser beam used for forming a polycrystalline semiconductor film is prevented by irradiating the laser beam onto an...
US20130005156 STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS  
Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on...
US20110115027 STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS  
Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on...
US20110284995 MICROMECHANICAL MEMBRANES AND RELATED STRUCTURES AND METHODS  
Micromechanical membranes suitable for formation of mechanical resonating structures are described, as well as methods for making such membranes. The membranes may be formed by forming cavities in...
US20060194454 Technique to radiation-harden trench refill oxides  
Oxide films are deposited under conditions generating a silicon-rich oxide in which silicon nanoclusters form either during deposition or during subsequent annealing. Such deposition conditions...
US20090133731 CRISS-CROSSED AND COALIGNED CARBON NANOTUBE-BASED FILMS  
Devices including nano-junctions made between aligned functionalized carbon nanotubes, and methods of aligning functionalized carbon nanotubes for the purpose of fabricating either coaligned or...
US20080311762 Semiconductor device surface roughness reduction  
Methods and apparatus relating to surface roughness reduction are described. In one embodiment, a particle beam may be directed onto the surface roughness of a semiconductor device to reduce the...
US20140094039 EDGE RING LIP  
Embodiments of the invention generally relate to a support ring to support a substrate in a process chamber. In one embodiment, the support ring comprises an inner ring, an outer ring connecting...
US20090130865 METHOD OF PATTERNING A LAYER USING A PELLICLE  
A method for patterning a layer on a semiconductor substrate includes forming a layer of a semiconductor substrate and exposing the layer to light. The light travels through a second pellicle that...
US20050208779 Imprint lithography process  
An imprint lithography process is used for the production of a semiconductor component. A polymeric gate dielectric layer (12) is structured in the absence of a resist solely by at least one...
US20090233456 IRRADIATION OPTICAL SYSTEM, IRRADIATION APPARATUS AND FABRICATION METHOD FOR SEMICONDUCTOR DEVICE  
An irradiation optical system includes: a first projection optical system for mixing a plurality of luminous fluxes outputted from a laser light source having a plurality of linearly arrayed light...
US20100184303 Method for revealing emergent dislocations in a germanium-base crystalline element  
The invention relates to a method for detecting defects, more particularly emergent dislocations of an element having at least one crystalline germanium-base superficial layer. The method...
US20120000529 METHOD AND SYSTEM FOR FORMING A PHOTOVOLTAIC CELL AND A PHOTOVOLTAIC CELL  
Disclosed is a photovoltaic cell, a method of forming the photovoltaic cell, and a system for forming the photovoltaic cell. The photovoltaic cell includes a plurality of layers, at least one...
US20150212419 Lithography System And Method For Haze Elimination  
The present disclosure provides an apparatus in semiconductor manufacturing. The apparatus includes a mask, a pellicle frame attached to the mask, and a pellicle joined to the pellicle frame...
US20150187597 METHOD TO IMPROVE SLIP RESISTANCE OF SILICON WAFERS  
By controlling the concentration and size of bulk micro defects (BMD) during the manufacture of an integrated circuit slip and associated yield loss due to slip may be eliminated. A process for...
US20070293012 REDUCTION OF SLIP AND PLASTIC DEFORMATIONS DURING ANNEALING BY THE USE OF ULTRA-FAST THERMAL SPIKES  
Exemplary embodiments provide methods for reducing and/or removing slip and plastic deformations in semiconductor materials by use of one or more ultra-fast thermal spike anneals. The ultra-fast...
US20110263138 SUBSTRATE PROCESSING CHAMBER WITH DIELECTRIC BARRIER DISCHARGE LAMP ASSEMBLY  
A thermal processing chamber with a dielectric barrier discharge (DBD) lamp assembly and a method for using the same are provided. In one embodiment, a thermal processing chamber includes a...
US20070293057 Method of direct coulomb explosion in laser ablation of semiconductor structures  
A new technique and Method of Direct Coulomb Explosion in Laser Ablation of Semiconductor Structures in semiconductor materials is disclosed. The Method of Direct Coulomb Explosion in Laser...
US20080176415 Wafer support pin for preventing slip dislocation during annealing of water and wafer annealing method using the same  
A wafer support pin has a front end contacted with a wafer such that the front end is flat or rounded. Thus, gravitational stress is minimized during annealing the wafer, thereby minimizing slip...
US20070254493 Integrated thermal unit having vertically arranged bake and chill plates  
An integrated thermal unit comprising a housing; a bake station positioned within the housing, the bake station comprising a bake plate configured to heat a substrate supported on a surface of the...
US20080166889 EDA METHODOLOGY FOR EXTENDING GHOST FEATURE BEYOND NOTCHED ACTIVE TO IMPROVE ADJACENT GATE CD CONTROL USING A TWO-PRINT-TWO-ETCH APPROACH  
In accordance with various embodiments, semiconductor devices and methods of forming semiconductor devices having non-rectangular active regions are provided. An exemplary method includes using a...
US20130299939 CHIP IDENTIFICATION PATTERN AND METHOD OF FORMING  
Various embodiments disclosed include methods of performing a double exposure process on a level of an integrated circuit (IC) chip to form an IC chip having an embedded electrically measurable...
US20070099439 ARRANGEMENT AND METHOD FOR FORMING ONE OR MORE SEPARATED SCORES IN A SURFACE OF A SUBSTRATE  
The present invention is directed to an arrangement for forming one or more separated scores in a surface of a substrate. The arrangement comprises a laser for providing a laser beam, optical...
US20080166890 High Pressure Hydrogen Annealing for Mosfet  
The present invention relates to a high pressure hydrogen annealing method for MOSFET semiconductor device, and more particularly, to effectively remove a supersaturated hydrogen on a high-k...
US20080119060 Inspection systems and methods  
Inspection systems and methods are disclosed. A preferred embodiment comprises an inspection system including a support for a reticle and a microscope including a lens system. The lens system...
US20110269316 Wafer Support Ring  
A wafer support ring and a method of using the same are disclosed herein. The support ring supports a wafer during a first processing operation. A top surface of the support ring is in contact...
US20110136348 PHONON-ENHANCED CRYSTAL GROWTH AND LATTICE HEALING  
A system for modifying dislocation distributions in semiconductor materials is provided. The system includes one or more vibrational sources for producing at least one excitation of vibrational...
US20100062562 Methods Utilizing Microwave Radiation During Formation Of Semiconductor Constructions  
Some embodiments include methods in which microwave radiation is used to activate dopant and/or increase crystallinity of semiconductor material during formation of a semiconductor construction....
US20090203230 Mask for crystallizing a semiconductor layer and method of crystallizing a semiconductor layer using the same  
A mask for crystallizing a semiconductor layer includes a plurality of first main-slit portions, a plurality of second main-slit portions, upper slit portion and lower slit portion. The first...
US20090221141 METHOD FOR PATTERNING CRYSTALLINE INDIUM TIN OXIDE USING FEMTOSECOND LASER  
A method for patterning crystalline indium tin oxide (ITO) using femtosecond laser is disclosed, which comprises steps of: (a) providing a substrate with an amorphous ITO layer thereon; (b)...
US20080014764 LOW TEMPERATURE, LONG TERM ANNEALING OF NICKEL CONTACTS TO LOWER INTERFACIAL RESISTANCE  
A method of annealing semiconductor devices to form substantially ohmic contact regions between a layer of wide band-gap semiconductor material and contact areas disposed thereon includes exposing...
US20080150165 SELECTIVE PROCESSING OF SEMICONDUCTOR NANOWIRES BY POLARIZED VISIBLE RADIATION  
Methods, systems, and apparatuses for annealing semiconductor nanowires and for fabricating electrical devices are provided. Nanowires are deposited on a substrate. A plurality of electrodes is...
US20100085081 INVERTER MANUFACTURING METHOD AND INVERTER  
To provide an enhancement-depletion (E/D) inverter which can be easily manufactured, in the present invention, a method of manufacturing an inverter which is composed of an oxide semiconductor in...
US20100084613 SEMICONDUCTOR DOPING PROCESS  
A doping process, including applying pressure to at least one first phase of a semiconductor containing an electrically inactive dopant and removing the pressure to cause at least one phase...
US20050272179 Three-dimensional lithographic fabrication technique  
Embodiments of a structure and embodiments of methods for fabricating structures provide three dimensional features defined by exposure to multiple wavelengths of light. In an embodiment, material...
US20130288487 METHOD AND SYSTEM FOR CONTROLLING A SPIKE ANNEAL PROCESS  
Provided is a method and system for controlling a spike anneal process on a substrate, comprising selecting one or more objectives, one or more absorbance layers, a technique of modifying...
US20080045040 Laser Spike Anneal With Plural Light Sources  
A semiconductor wafer is preheated in advance of laser annealing by directing focused energy from a first energy source onto a local area of the wafer. High power laser light from a second energy...
US20100233858 METHOD OF PREVENTING GENERATION OF ARC DURING RAPID ANNEALING BY JOULE HEATING  
Disclosed herein is a rapid annealing method in a mixed structure composed of a heat treatment-requiring material, dielectric layer and conductive layer, comprising that during rapid annealing on...
US20080226272 HEATING APPARATUS, HEAT TREATMENT APPARATUS, COMPUTER PROGRAM AND STORAGE MEDIUM  
A heating apparatus for heating a target object W is provided with a plurality of heating light sources, including LED elements for applying heating light having a wavelength within a range from...