|
Match
|
Document |
Document Title |
|
|
US20150037979 |
CONFORMAL SIDEWALL PASSIVATION
A method for etching features into an etch layer in a stack disposed below a patterned mask with mask features is provided. Coating providing molecules are provided. The coating providing... |
|
|
US20120108067 |
Edge Bead Remover For Coatings
The invention relates to an edge bead remover composition for an organic film disposed on a substrate surface, comprising an organic solvent and at least one polymer having a contact angle with... |
|
|
US20120083124 |
Method of Patterning NAND Strings Using Perpendicular SRAF
A lithography mask includes a plurality of patterning features formed on a mask substrate and a first plurality of sub-resolution assist features (SRAFs) formed substantially perpendicular to the... |
|
|
US20150145070 |
MERGING LITHOGRAPHY PROCESSES FOR GATE PATTERNING
Methods for fabricating devices on a die, and devices on a die. A method may include patterning a first region to create a first gate having a first gate length and a first contacted polysilicon... |
|
|
US20100330790 |
TECHNIQUE FOR EXPOSING A PLACEHOLDER MATERIAL IN A REPLACEMENT GATE APPROACH BY MODIFYING A REMOVAL RATE OF STRESSED DIELECTRIC OVERLAYERS
In a replacement gate approach, the sacrificial gate material is exposed on the basis of enhanced process uniformity, for instance during a wet chemical etch step or a CMP process, by forming a... |
|
|
US20130095662 |
INTEGRATED CIRCUIT METHOD WITH TRIPLE PATTERNING
The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of IC features. The method includes... |
|
|
US20120190203 |
METHOD AND APPARATUS FOR ANGULAR HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION
Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second... |
|
|
US20120094478 |
RESIST FEATURE AND REMOVABLE SPACER PITCH DOUBLING PATTERNING METHOD FOR PILLAR STRUCTURES
A method of making a semiconductor device includes forming a layer over a substrate, forming a plurality of spaced apart features of imagable material over the layer, forming sidewall spacers on... |
|
|
US20120100719 |
METHOD FOR MAKING A PLANAR MEMBRANE
A method for determining a minimum tension compensation stress which will have a membrane of a thickness of less than or equal to one micrometer, secured to a frame, having, in the absence of any... |
|
|
US20130099260 |
RESIST STRIPPING COMPOSITION AND METHOD OF STRIPPING RESIST USING THE SAME
Disclosed herein is a resist stripping composition, which has an excellent ability of stripping a residual resist remaining after dry or wet etching at the tune of forming patterns in a process of... |
|
|
US20150228497 |
Plasma Method for Reducing Post-Lithography Line Width Roughness
The present disclosure is related to a method for treating a photoresist structure on a substrate, the method comprising producing one or more resist structures on a substrate, introducing the... |
|
|
US20120223418 |
SOLUTION PROCESSIBLE HARDMASKS FOR HIGH RESOLUTION LITHOGRAPHY
Solution processible hardmasks are described that can be formed from aqueous precursor solutions comprising polyoxometal clusters and anions, such as polyatomic anions. The solution processible... |
|
|
US20130307578 |
TAMPER RESISTANT IC
According to an aspect of the invention an integrated circuit is conceived which comprises a physical unclonable function which is at least partially implemented in a passivation layer of said... |
|
|
US20140199844 |
ARRAY DESCRIPTION SYSTEM FOR LARGE PATTERNS
A method for describing an array of elements includes the steps of providing an array description system that includes a library of possible alternative designations; and describing the array of... |
|
|
US20090061631 |
GATE REPLACEMENT WITH TOP OXIDE REGROWTH FOR THE TOP OXIDE IMPROVEMENT
Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are... |
|
|
US20140310914 |
MEMS HINGES WITH ENHANCED ROTATABILITY
A mechanical device includes a long, narrow element made of a rigid, elastic material. A rigid frame is configured to anchor at least one end of the element, which is attached to the frame, and to... |
|
|
US20150021743 |
UNIFORM ROUGHNESS ON BACKSIDE OF A WAFER
Substrates (wafers) with uniform backside roughness and methods of manufacture are disclosed. The method includes forming a material on a backside of a wafer. The method further includes... |
|
|
US20090090974 |
DUAL STRESS LINER STRUCTURE HAVING SUBSTANTIALLY PLANAR INTERFACE BETWEEN LINERS AND RELATED METHOD
A dual stress liner structure having a substantially planar interface between liners and a related method are disclosed. In one embodiment, a dual stress liner structure may include a tensile... |
|
|
US20110001198 |
MEMS DEVICE AND INTERPOSER AND METHOD FOR INTEGRATING MEMS DEVICE AND INTERPOSER
A method for producing Microelectromechanical Systems (MEMS) and related devices using Silicon-On-Insulator (SOI) wafer includes providing an SOI wafer, performing a mesa etch to at least... |
|
|
US20150097271 |
SELF-HEALING CRACK STOP STRUCTURE
A self-healing crack stop structure and methods of manufacture are disclosed herein. The structure comprises a crack stop structure formed in one or more dielectric layers and surrounding an... |
|
|
US20080214007 |
METHOD FOR REMOVING DIAMOND LIKE CARBON RESIDUE FROM A DEPOSITION/ETCH CHAMBER USING A PLASMA CLEAN
Provided is a method for removing diamond like carbon residue from a deposition chamber. This method, in one embodiment, may include subjecting a deposition chamber including diamond like carbon... |
|
|
US20120034783 |
MANUFACTURING INTEGRATED CIRCUIT COMPONENTS HAVING MULTIPLE GATE OXIDATIONS
STI divot formation is minimized and STI field height mismatch between different regions is eliminated. A nitride cover layer (150) having a thickness less than 150 then a oxide cover layer (160)... |
|
|
US20090116675 |
MEMS DIAPHRAGM STRUCTURE AND METHOD FOR FORMING THE SAME
A diaphragm (14) is formed using MEMS technology. The diaphragm (14) has a hinge structure, and at least one of a hinge upper corner portion and a hinge lower corner portion of the diaphragm (14)... |
|
|
US20120098133 |
STRUCTURE AND METALLIZATION PROCESS FOR ADVANCED TECHNOLOGY NODES
The problem of poor adherence of a dielectric coating on a patterned metal structure can be solved by forming an adhesion layer on exposed surfaces of such metal structure prior to deposition of... |
|
|
US20140141615 |
METHOD OF FORMING PATTERNED FILM ON A BOTTOM AND A TOP-SURFACE OF A DEEP TRENCH
A method of forming a patterned film on both a bottom and a top-surface of a deep trench is disclosed. The method includes the steps of: 1) providing a substrate having a deep trench formed... |
|
|
US20110018054 |
Method for Preventing Gate Oxide Damage of a Trench MOSFET during Wafer Processing while Adding an ESD Protection Module Atop
A method and device structure are disclosed for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET. The ESD... |
|
|
US20100297848 |
ETCHING OF TUNGSTEN SELECTIVE TO TITANIUM NITRIDE
The present invention in one embodiment provides an etch method that includes providing a structure including a tungsten (W) portion and a titanium nitride (TiN) portion; applying a first etch... |
|
|
US20110104900 |
Alkaline Rinse Agents For Use In Lithographic Patterning
Lithographic patterning methods involve the formation of a (one or more) metal oxide capping layer, which is rinsed with an aqueous alkaline solution as part of the method. The rinse solution does... |
|
|
US20130052827 |
SELECTIVE SUPPRESSION OF DRY-ETCH RATE OF MATERIALS CONTAINING BOTH SILICON AND OXYGEN
A method of suppressing the etch rate for exposed silicon-and-oxygen-containing material on patterned heterogeneous structures is described and includes a two stage remote plasma etch. Examples of... |
|
|
US20130040412 |
METHOD OF FORMING SILICON NANOWIRES AND METHOD OF FABRICATING LITHIUM SECONDARY BATTERY USING THE SAME
A method of preparing a silicon nanowire and a method of fabricating a lithium secondary battery including the silicon nanowire are provided. The method of preparing a silicon nanowire may include... |
|
|
US20140054753 |
NANO-MESHED STRUCTURE PATTERN ON SAPPHIRE SUBSTRATE BY METAL SELF-ARRANGEMENT
The present disclosure provides a nano-meshed patterned substrate and a method of forming the same. In an embodiment, a metal layer is formed on a substrate, and a heat treatment is performed on... |
|
|
US20090108306 |
UNIFORM RECESS OF A MATERIAL IN A TRENCH INDEPENDENT OF INCOMING TOPOGRAPHY
Columnar elements which extend to varying heights above a major surface of a substrate, e.g., polysilicon studs within trenches in the substrate, are recessed to a uniform depth below the major... |
|
|
US20090170324 |
Reducing adherence in a MEMS device
In one embodiment, an apparatus for reducing adherence in a micro-electromechanical system (MEMS) device comprises a substrate. A MEMS is disposed outwardly from the substrate. The MEMS comprises... |
|
|
US20060134917 |
Reduction of etch mask feature critical dimensions
A method for forming features in an etch layer in an etch stack with an etch mask over the etch layer, wherein the etch mask has etch mask features with sidewalls, where the etch mask features... |
|
|
US20110151668 |
PITCH DIVISION PATTERNING TECHNIQUES
Embodiments of the invention comprise pitch division techniques to extend the capabilities of lithographic techniques beyond their minimum pitch. The pitch division techniques described herein... |
|
|
US20130049158 |
FORMATION OF METAL NANOSPHERES AND MICROSPHERES
Hemispheres and spheres are formed and employed for a plurality of applications. Hemispheres are employed to form a substrate having an upper surface and a lower surface. The upper surface... |
|
|
US20090149025 |
Remover Compositions
A remover composition containing 1,3-propanediamine (a), 1-hydroxyethylidene-1,1-diphosphonic acid (b) and water, wherein the remover composition contains the component (a) in an amount of from... |
|
|
US20120238096 |
METHOD AND APPARATUS FOR INSPECTING A REFLECTIVE LITHOGRAPHIC MASK BLANK AND IMPROVING MASK QUALITY
An EUV integrated circuit fabrication method and system EUV that includes blank inspection, defect characterization, simulation, pattern compensation, modification of the mask writer database,... |
|
|
US20090273035 |
METHOD FOR SELECTIVELY REMOVING A SPACER IN A DUAL STRESS LINER APPROACH
By integrating a spacer removal process into the sequence for patterning a first stress-inducing material during a dual stress liner approach, the sidewall spacer structure for one type of... |
|
|
US20130059440 |
SELECTIVE SUPPRESSION OF DRY-ETCH RATE OF MATERIALS CONTAINING BOTH SILICON AND NITROGEN
A method of suppressing the etch rate for exposed silicon-and-nitrogen-containing material on patterned heterogeneous structures is described and includes a two stage remote plasma etch. The etch... |
|
|
US20130017682 |
Overburden Removal For Pore Fill Integration Approach
In one exemplary embodiment of the invention, a method includes: providing a structure having a first layer overlying a substrate, where the first layer includes a dielectric material having a... |
|
|
US20110097904 |
METHOD FOR REPAIRING LOW-K DIELECTRIC DAMAGE
A method for repairing damage to a silicon based low-k dielectric layer with organic compounds, where damage replaces a methyl attached to silicon with a hydroxyl attached to silicon is provided.... |
|
|
US20110183520 |
Method for Removing Copper Oxide Layer
The invention is directed to a method for removing copper oxide from a copper surface to provide a clean copper surface, wherein the method involves exposing the copper surface containing copper... |
|
|
US20120289049 |
COPPER OXIDE REMOVAL TECHNIQUES
A method for the removal of copper oxide from a copper and dielectric containing structure of a semiconductor chip is provided. The copper and dielectric containing structure may be planarized by... |
|
|
US20150040983 |
ACIDIC ETCHING PROCESS FOR SI WAFERS
The present invention relates to a method for acidic surface etching of a silicon wafer, such as those used for solar cells, comprising contacting at least one surface of a silicon wafer as cut... |
|
|
US20100001255 |
SELECTIVE NANOTUBE FORMATION AND RELATED DEVICES
Nanotube electronic devices exhibit selective affinity to disparate nanotube types. According to an example embodiment, a semiconductor device exhibits a treated substrate that selectively... |
|
|
US20100297847 |
Method of forming sub-lithographic features using directed self-assembly of polymers
Methods involving the self-assembly of block copolymers are described herein, in which by beginning with openings (in one or more substrates) that have a targeted CD (critical dimension), holes... |
|
|
US20100207249 |
WAFER INCLUDING A REINFORCING FLANGE FORMED UPRIGHT AT A PERIPHERY AND METHOD FOR MANUFACTURING THE SAME
A wafer with an orientation notch being cut in a portion of its circumference, the wafer includes: a reinforcing flange formed upright at periphery; and a thin section surrounded by the... |
|
|
US20130005147 |
METHOD OF REDUCING CRITICAL DIMENSION PROCESS BIAS DIFFERENCES BETWEEN NARROW AND WIDE DAMASCENE WIRES
A method including forming an organic polymer layer (OPL) on a substrate; forming a patterned photoresist layer having a first opening and a second opening over the OPL, the second opening wider... |
|
|
US20140117488 |
PATTERN DECOMPOSITION LITHOGRAPHY TECHNIQUES
Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target features that, when aggregated,... |