AcclaimIP-ad

Match Document Document Title
US20050124161 Growth and integration of epitaxial gallium nitride films with silicon-based devices  
Epitaxial gallium nitride is grown on a silicon substrate while reducing or suppressing the formation of a buffer layer. The gallium nitride may be grown directly on the silicon substrate, for...
US20120126338 CROSS-HAIR CELL DEVICES AND METHODS FOR MANUFACTURING THE SAME  
Systems and methods are disclosed for manufacturing grounded gate cross-hair cells and standard cross-hair cells of fin field-effect transistors (finFETs). In one embodiment, a process may include...
US20120108064 POLISHING COMPOSITION FOR SILICON WAFERS  
A polishing composition for a silicon wafer includes a macromolecular compound, an abrasive, and an aqueous medium. The macromolecular compound includes a constitutional unit (a1) represented by...
US20130143403 TEXTURE-ETCHANT COMPOSITION FOR CRYSTALLINE SILICON WAFER AND METHOD FOR TEXTURE-ETCHING (1)  
Disclosed herein is an etching composition for texturing a crystalline silicon wafer, comprising, based on a total amount of the composition: (A) 0.1 to 20 wt % of an alkaline compound; (B) 0.1 to...
US20130299967 WSP DIE HAVING REDISTRIBUTION LAYER CAPTURE PAD WITH AT LEAST ONE VOID  
A MP die with a redistribution layer (“RDL”) capture pad having at least one void therein and having an RDL capture pad outer peripheral edge and an under bump metal (“UBM”) pad positioned above...
US20080187870 METHOD FOR FORMING PHOTORESIST PATTERN, METHOD FOR MANUFACTURING DISPLAY PANEL, AND METHOD FOR MANUFACTURING DISPLAY DEVICE  
A method for forming a photoresist pattern includes forming a photoresist, and forming a photoresist pattern having a step portion by performing a light exposure process a different number of...
US20080251868 Standard component for calibration and electron-beam system using the same  
The invention provides a standard component for calibration that enables a calibration position to be easily specified in order to calibrate accurately a scale factor in the electron-beam system,...
US20050032370 Graphite material for synthesizing semiconductor diamond and semiconductor diamond produced by using the same  
A method for producing a semiconductor diamond containing boron by the high pressure synthesis method, wherein a graphite material to be converted to the semiconductor diamond is mixed with boron...
US20130228283 Temperature Control in RF Chamber with Heater and Air Amplifier  
Systems, methods, and computer programs are presented for controlling the temperature of a window in a semiconductor manufacturing chamber. One apparatus includes an air amplifier, a plenum, a...
US20110084332 TRENCH TERMINATION STRUCTURE  
A trench MOS device includes a base semiconductor substrate, an epitaxial layer grown on the base semiconductor substrate, a first trench in the epitaxial layer, and a stepped trench comprising a...
US20100327260 Single Electron Transistor Operating at Room Temperature and Manufacturing Method for Same  
The present invention relates to a single electron transistor operating at room temperature and a manufacturing method for same. More particularly, the present invention relates to a single...
US20050090104 Slurry compositions for chemical mechanical polishing of copper and barrier films  
CMP slurries comprising at least an abrasive, at least an organic phosphonate, at least an oxidizer, and water are disclosed. The slurries can optionally include corrosion inhibitors, surfactants,...
US20140167045 TEST PATTERN FOR TRENCH POLY OVER-ETCHED STEP AND FORMATION METHOD THEREOF  
A test pattern for testing a trench POLY over-etched step is provided. The test pattern is a trench (14) formed on a substrate (1); the trench (14) comprises a bottom surface and two side surfaces...
US20060264049 Spin-printing of etchants and modifiers  
The present invention is directed to processes for printing compositions containing etchants or modifiers onto surfaces by spinning a filament from a viscoelastic polymer solution containing an...
US20060057846 Composition for use as sanitary earthenware material, method for production thereof, method for manufacturing sanitary earthenware using said composition  
Disclosed are a composition for a sanitary ware body for use in slip casting, possessing excellent long-term storage stability, transportability and slurry regeneration, a production process of...
US20130040454 Annealing Copper Interconnects  
A method for modifying the chemistry or microstructure of silicon-based technology via an annealing process is provided. The method includes depositing a reactive material layer within a selected...
US20060240670 Etching of algainassb  
The present invention relates to a wet acid etchant for wet acid etching of intrinsic, n-doped or p-doped Al1−x−zGaxInzAs1−ySby with 0
US20090047773 METHOD OF FORMING STABLE FUNCTIONALIZED NANOPARTICLES  
A novel top-down procedure for synthesis of stable passivated nanoparticles uses a one-step mechanochemical process to form and passivate the nanoparticles. High-energy ball milling (HEBM) can...
US20060030156 Abrasive conductive polishing article for electrochemical mechanical polishing  
Articles of manufacture and processes for planarizing a layer on a substrate are provided. In one aspect, a process is provided for manufacturing a polishing article comprising combining a...
US20120168915 RELIABLE INTERCONNECT INTEGRATION SCHEME  
Embodiments relate to a method for forming reliable interconnects by preparing a substrate with a dielectric layer, processing the dielectric layer to serve as an IMD layer, wherein the IMD layer...
US20110263125 METHOD OF FORMING MARK IN IC-FABRICATING PROCESS  
A method of forming a mark in an IC fabricating process is described. Two parts of the mark each including a plurality of linear patterns are respectively defined by two exposure steps that either...
US20070105383 PHOTOACTIVE ADHESION PROMOTER IN A SLAM  
A semiconductor process technique to help reduce semiconductor process effects, such as undesired line edge roughness, insufficient lithographical resolution, and limited depth of focus problems...
US20150017805 WAFER PROCESSING APPARATUS HAVING INDEPENDENTLY ROTATABLE WAFER SUPPORT AND PROCESSING DISH  
An apparatus for processing a wafer is disclosed that includes a wafer support and a processing base. The wafer support is configured to support a wafer in a processing position, and to rotate the...
US20080179010 Bevel etcher with vacuum chuck  
A bevel etcher incorporating a vacuum chuck used for cleaning the bevel edge and for reducing the bending curvature of a semiconductor substrate. The bevel etcher includes a vacuum chuck and a...
US20050101133 Method for making negative thermal expansion material zirconium tungstate  
A method for making negative thermal expansion material zirconium tungstate (ZrW2O8) comprise: (a)forming a gel wrapped solid product comprising a water-soluble zirconium compound, preferably...
US20070215280 Semiconductor surface processing  
A semiconductor surface processing method in one example comprises disposing a polishing pad in rotating engagement with a semiconductor wafer to be polished, dripping a first polishing solution...
US20090111205 Method of seperating two material systems  
An embodiment of this invention discloses a method of separating two material systems, which comprises steps of providing a bulk sapphire; forming a nitride system on the bulk sapphire; forming at...
US20130037915 Method and Apparatus for Providing a Layout Defining a Structure to be Patterned onto a Substrate  
A method provides a layout defining a structure to be patterned onto a substrate. The structure is registered with a predefined grid of the layout. The method includes locally stretching the grid...
US20070072421 Method to passivate defects in integrated circuits  
Defects in an integrated circuit are electrically passivated. A hydrogen diffusion blocking film is placed on the integrated circuit. Atomic hydrogen is implanted through the hydrogen diffusion...
US20060292883 ETCHING OF SILICON NITRIDE WITH IMPROVED NITRIDE-TO-OXIDE SELECTIVITY UTILIZING HALOGEN BROMIDE/CHLORINE PLASMA  
A method of manufacturing a semiconductor device is disclosed. A gate is formed on a semiconductor substrate. A gate oxide is formed between the gate and the semiconductor substrate. A silicon...
US20100093171 FABRICATION CUBIC BORON NITRIDE CONE-MICROSTRUCTURES AND THEIR ARRAYS  
A conical structure of cubic Boron Nitride (cBN) is formed on a diamond layered substrate. A method of forming the cBN structure includes steps of (a) forming diamond nuclei on a substrate, (b)...
US20090186483 ETCHING AMOUNT CALCULATING METHOD, STORAGE MEDIUM, AND ETCHING AMOUNT CALCULATING APPARATUS  
An etching amount calculating method that can stably and accurately calculate the amount of etching even if a disturbance is added. Superposed interference light resulting from superposition of...
US20130143391 REACTED LAYER FOR IMPROVING THICKNESS UNIFORMITY OF STRAINED STRUCTURES  
Methods are disclosed of forming and removing a reacted layer on a surface of a recess to provide mechanisms for improving thickness uniformity of a semiconductor material formed in the recess....
US20110151669 Release Accumulative Charges by Tuning ESC Voltages in Via-Etchers  
A method of forming an integrated circuit structure on a wafer includes providing a first etcher comprising a first electrostatic chuck (ESC); placing the wafer on the first ESC; and forming a via...
US20140034497 CHIP SET-UP AND HIGH-ACCURACY NUCLEIC ACID SEQUENCING  
The present disclosure provides devices, systems and methods for sequencing nucleic acid molecules. Nucleic acid molecules can be sequenced with a high accuracy (e.g., greater than 97% in a single...
US20050170650 Electroless palladium nitrate activation prior to cobalt-alloy deposition  
In one embodiment, a method for activating a metal layer prior to depositing a cobalt-containing capping layer is provided which includes exposing the metal layer to an electroless activation...
US20060175012 Semiconductor fabrication equipment and method for controlling pressure  
Provided are semiconductor fabrication equipment and a related method of controlling pressure in a process chamber associated with the equipment. Multiple connected vacuum lines, each having a...
US20090170316 Double patterning with single hard mask  
In general, in one aspect, a method includes forming a hard mask on a semiconductor substrate. A first resist layer is patterned on the hard mask as a first plurality of lines separated by a first...
US20080254627 METHOD FOR ADJUSTING FEATURE SIZE AND POSITION  
Variations in the pitch of features formed using pitch multiplication are minimized by separately forming at least two sets of spacers. Mandrels are formed and the positions of their sidewalls are...
US20070049030 Pitch multiplication spacers and methods of forming the same  
Spacers in a pitch multiplication process are formed without performing a spacer etch. Rather, the mandrels are formed over a substrate and then the sides of the mandrels are reacted, e.g., in an...
US20150050811 CRITICAL DIMENSION AND PATTERN RECOGNITION STRUCTURES FOR DEVICES MANUFACTURED USING DOUBLE PATTERNING TECHNIQUES  
An illustrative test structure is disclosed herein that includes a plurality of first line features and a plurality of second line features. In this embodiment, each of the second line features...
US20130207108 Critical Dimension and Pattern Recognition Structures for Devices Manufactured Using Double Patterning Techniques  
An illustrative test structure is disclosed herein that includes a plurality of first line features and a plurality of second line features. In this embodiment, each of the second line features...
US20130130500 COMPOSITION FOR REMOVAL OF NICKEL-PLATINUM ALLOY-BASED METALS  
A composition for the removal of nickel-platinum alloy metal, said composition being characterised by including 3-55 mass % of at least one kind selected from the group consisting of hydrochloric...
US20080230763 Metallic Nanospheres Embedded in Nanowires Initiated on Nanostructures and Methods for Synthesis Thereof  
A nanostructure includes a nanowire having metallic spheres formed therein, the spheres being characterized as having at least one of about a uniform diameter and about a uniform spacing there...
US20070190787 Method for etching silicon-germanium in the presence of silicon  
A method for selectively etching single-crystal silicon-germanium in the presence of single-crystal silicon, including a chemical etch based on hydrochloric acid in gaseous phase at a temperature...
US20070281477 Process for etching tungsten silicide overlying polysilicon particularly in a flash memory  
A method of plasma etching tungsten silicide over polysilicon particularly useful in fabricating flash memory having both a densely packed area and an open (iso) area requiring a long over etch...
US20090160040 LOW TEMPERATURE CERAMIC MICROELECTROMECHANICAL STRUCTURES  
A method of providing microelectromechanical structures (MEMS) that are compatible with silicon CMOS electronics is provided. The method provides for processing and manufacturing is steps limiting...
US20090324162 CMOS COMPATIBLE INTEGRATED DIELECTRIC OPTICAL WAVEGUIDE COUPLER AND FABRICATION  
An optoelectronic circuit fabrication method and integrated circuit apparatus fabricated therewith. Integrated circuits are fabricated with an integral optical coupling transition to efficiently...
US20060283552 Plasma confinement rings including RF absorbing material for reducing polymer deposition  
Plasma confinement rings are adapted to reach sufficiently high temperatures on plasma-exposed surfaces of the rings to substantially reduce polymer deposition on those surfaces. The plasma...
US20130224953 ABATEMENT AND STRIP PROCESS CHAMBER IN A LOAD LOCK CONFIGURATION  
Embodiments of the present invention a load lock chamber including two or more isolated chamber volumes, wherein one chamber volume is configured for processing a substrate and another chamber...