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US20080273410 Tungsten digitlines  
Methods, devices, and systems for using and forming tungsten digitlines have been described. The tungsten digitlines formed according to embodiments of the present disclosure can be formed with a...
US20090278260 REDUNDANCY DESIGN WITH ELECTRO-MIGRATION IMMUNITY AND METHOD OF MANUFACTURE  
An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, a design structure of the IC interconnect and a method of manufacture of the IC...
US20050026408 Preventing silicide formation at the gate electrode in a replacement metal gate technology  
A hard mask may be formed and maintained over a polysilicon gate structure in a metal gate replacement technology. The maintenance of the hard mask, such as a nitride hard mask, may protect the...
US20150037973 METHOD FOR CAPPING COPPER INTERCONNECT LINES  
A method of forming a capping layer over copper containing contacts in a dielectric layer with a liner comprising a noble metal liner around the copper containing contacts is provided. An...
US20090163022 TFT ARRAY PANEL  
Multi-layered wiring for a larger flat panel display is formed by depositing molybdenum on a substrate in presence of a precursor gas containing at least one oxygen, nitrogen and carbon to form a...
US20080217775 Method of forming contact plugs for eliminating tungsten seam issue  
A method of forming a contact plug of an eDRAM device includes the following steps: forming a tungsten layer with tungsten seam on a dielectric layer to fill a contact hole; removing the tungsten...
US20110250749 INTERCONNECTS WITH IMPROVED ELECTROMIGRATION RELIABILITY  
An interconnect structure in a semiconductor device may be formed to include a number of segments. Each segment may include a first metal. A barrier structure may be located between the plurality...
US20050020059 Method for forming aluminum-containing interconnect  
A method for forming an aluminum-containing interconnect is provided. The method includes providing a substrate with a contact region. A first barrier layer, an aluminum-containing conductive...
US20070173059 PROCESS KIT COMPONENTS FOR TITANIUM SPUTTERING CHAMBER  
A process kit for a sputtering chamber comprises a deposition ring, cover ring, and a shield assembly, for placement about a substrate support in a sputtering chamber. The deposition ring...
US20120038050 SPUTTERING TARGET  
A sputtering target consists of high purity Nb of which Ta content is 3000 ppm or less and oxygen content is 200 ppm or less. Dispersion of the Ta content in all the sputtering target is within...
US20060024959 Thin tungsten silicide layer deposition and gate metal integration  
A method for depositing layers of a gate electrode is provided. The method includes depositing a doped polysilicon layer, a thin tungsten silicide layer, and a metal layer. In one aspect, the...
US20080308942 SEMICONDUCTOR WIRING STRUCTURES INCLUDING DIELECTRIC CAP WITHIN METAL CAP LAYER  
Semiconductor wiring structures including a dielectric layer having a metal wiring line therein, a via extending downwardly from the metal wiring line, a metal cap layer over the metal wiring...
US20060046478 Method for forming tungsten nitride film  
Disclosed herein is a method for forming a tungsten nitride film by introducing a tungsten precursor and a hydrazine derivative as a nitrogen source in a specific ratio into a reaction chamber,...
US20110108990 Capping of Copper Interconnect Lines in Integrated Circuit Devices  
A method for capping lines includes forming a metal film layer on a copper line by a selective deposition process, the copper line disposed in a dielectric substrate, wherein the depositing also...
US20100084766 SURFACE REPAIR STRUCTURE AND PROCESS FOR INTERCONNECT APPLICATIONS  
Semiconductor interconnect structures including a surface-repair material, e.g., a noble metal or noble metal alloy, that fills hollow-metal related defects located within a conductive material...
US20100267230 METHOD FOR FORMING TUNGSTEN CONTACTS AND INTERCONNECTS WITH SMALL CRITICAL DIMENSIONS  
Provided are methods of void-free tungsten fill of high aspect ratio features. According to various embodiments, the methods involve a reduced temperature chemical vapor deposition (CVD) process...
US20060001162 Nitride and polysilicon interface with titanium layer  
A conductive structure in an integrated circuit (12), and a method of forming the structure, is provided that includes a polysilicon layer (30), a thin layer containing titanium over the...
US20070184652 Method for preparing a metal feature surface prior to electroless metal deposition  
The present invention provides a method for manufacturing an interconnect and an integrated circuit. The method for manufacturing the interconnect, in one embodiment, includes forming a first...
US20130037956 THIN FILM STRUCTURE FOR HIGH DENSITY INDUCTORS AND REDISTRIBUTION IN WAFER LEVEL PACKAGING  
Disclosed is a package that includes a wafer substrate and a metal stack seed layer. The metal stack seed layer includes a titanium thin film outer layer. A resist layer is provided in contact...
US20070164440 Semiconductor device, dicing saw and method for manufacturing the semiconductor device  
A first interlayer insulating film and a second interlayer insulating film are formed on a semiconductor substrate and first Cu interconnections are formed in the first interlayer insulating film...
US20070218683 Method of integrating PEALD Ta- containing films into Cu metallization  
A method for forming a modified TaC or TaCN film that may be utilized as a barrier film for Cu metallization. The method includes disposing a substrate in a process chamber of a plasma enhanced...
US20060292863 PREVENTING DAMAGE TO METAL USING CLUSTERED PROCESSING AND AT LEAST PARTIALLY SACRIFICIAL ENCAPSULATION  
Methods are disclosed for metal encapsulation for preventing exposure of metal during semiconductor processing. In one embodiment, the method includes forming an opening in a structure exposing a...
US20090184425 Conductive line structure and the method of forming the same  
The conductive line structure of a semiconductor device including a base; at least one patterned conductive layer formed over the base; a conductive line formed over the at least one patterned...
US20120329270 SURFACE REPAIR STRUCTURE AND PROCESS FOR INTERCONNECT APPLICATIONS  
A method is provided which includes providing a dielectric material having a dielectric constant of about 4.0 or less and at least one conductive material embedded therein, the at least one...
US20070026671 Method of forming low resistance tungsten films  
Provided is a method for forming low resistance metal films in which an underlying film, for example, a barrier layer or an adhesion layer, is formed on a semiconductor substrate. The underlying...
US20130049074 METHODS FOR FORMING CONNECTIONS TO A MEMORY ARRAY AND PERIPHERY  
Methods are disclosed for forming connections to a memory array and a periphery of the array. The methods include forming stacks of conductive materials on the array and the periphery and forming...
US20120319282 Reliable Packaging and Interconnect Structures  
Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the...
US20100096756 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME  
A semiconductor device has a multilayer interconnection including a copper interconnection film formed in a predetermined area within an insulating film, a liner film, and a high-melting-point...
US20150228532 Air Gap Formation Between Bit Lines with Top Protection  
Air gaps are formed between bit lines by etching to remove sacrificial material from between bit lines. Bit lines are protected from etch damage. Sacrificial material may be selectively oxidized...
US20120068265 WIRING LAYER STRUCTURE AND PROCESS FOR MANUFACTURE THEREOF  
This wiring layer structure includes: an underlying substrate of a semiconductor substrate or a glass substrate; an oxygen-containing Cu layer or an oxygen-containing Cu alloy layer which is...
US20070202692 Method for forming silicide and method for fabricating semiconductor device  
A method for forming silicide includes the steps of: forming a nickel film on a silicon layer (or a silicon substrate); introducing nitrogen into at least one of the nickel film and the interface...
US20100052176 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF  
A semiconductor device includes a first wiring extending in a first direction and a second wiring extending in a second direction which crosses the first direction and being disposed with a space...
US20050186785 Device manufacturing method and substrate  
A method of producing a T-gate in a single stage exposure process using electromagnetic radiation is disclosed.
US20070066060 Semiconductor devices and fabrication methods thereof  
Semiconductor devices and fabrication methods thereof. An opening is formed in a first dielectric layer, exposing an active region of the transistor, and an tungsten-containing barrier is...
US20070072378 Method of manufacturing metal-oxide-semiconductor transistor devices  
A method of manufacturing a metal-oxide-semiconductor transistor device is disclosed. In the method, a silicon nitride spacer is formed and will be removed after an ion implantation process used...
US20080128913 TUNGSTEN INTERCONNECT SUPER STRUCTURE FOR SEMICONDUCTOR POWER DEVICES  
In one embodiment, the disclosure relates to a method for forming a semiconductor power device by depositing a first layer of TiW on a gate region and a source region, depositing a second layer of...
US20130193489 INTEGRATED CIRCUITS INCLUDING COPPER LOCAL INTERCONNECTS AND METHODS FOR THE MANUFACTURE THEREOF  
Embodiments of a method for manufacturing an integrated circuit are provided. In one embodiment, a partially-fabricated integrated circuit is produced including a semiconductor substrate having...
US20070252277 SEMICONDUCTOR DEVICES AND FABRICATION METHOD THEREOF  
A semiconductor device. The semiconductor device includes a substrate, a dielectric layer formed thereon, an opening formed in the dielectric layer, a first barrier layer overlying the sidewall of...
US20070010073 Method of forming a MOS device having a strained channel region  
A method of forming a semiconductor device comprising providing a substrate comprising a first device region, implanting a source/drain region in the first device region, forming a strained...
US20080188076 Method for fabricating semiconductor device  
A trench is formed in an interlayer dielectric formed on a substrate, then a barrier seed film is formed to cover the interlayer dielectric and the inner walls of the trench, and copper is...
US20070042600 Method for fabricating semiconductor device  
In a Cu interconnect process, an organic-based low-dielectric-constant interlayer film is formed, and then a protective film is deposited on the side and back surfaces of a wafer bevel and the...
US20100255674 METHOD OF FORMING CONTACT STRUCTURE  
Provided is a method of forming a contact structure. The method includes forming a conductive pattern on a substrate. An interlayer insulating layer covering the conductive pattern is formed. The...
US20100105169 SEMICONDUCTOR CHIP HAVING VIA ELECTRODES AND STACKED SEMICONDUCTOR CHIPS INTERCONNECTED BY THE VIA ELECTRODES  
A semiconductor device includes a semiconductor substrate and a via electrode. The via electrode has a first portion on the substrate and extends towards the substrate and has a plurality of...
US20100087060 METHODS OF FORMING SEMICONDUCTOR STRUCTURES  
The present invention relates to methods of forming semiconductor structures. The methods may include disposing electrically conductive material within an opening in a first dielectric material,...
US20090008777 INTER-CONNECTING STRUCTURE FOR SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF THE SAME  
An interconnecting structure for a semiconductor die assembly, comprising: a substrate with pre-formed wiring circuit formed therein; a die having contact pads on an active surface; an adhesive...
US20080045009 METHOD AND APPARATUS FOR SIMULTANEOUSLY REMOVING MULTIPLE CONDUCTIVE MATERIALS FROM MICROELECTRONIC SUBSTRATES  
A method and apparatus for simultaneously removing conductive materials from a microelectronic substrate. A method in accordance with one embodiment of the invention includes contacting a surface...
US20050087873 Method and structure for selective surface passivation  
Method and structure for passivating conductive material are disclosed. Atomic layer deposition of a thin passivation layer such as titanium nitride upon a conductive layer comprising a material...
US20150311157 NANOTUBE STRUCTURE BASED METAL DAMASCENE PROCESS  
In various embodiments a method for manufacturing a metallization layer on a substrate is provided, wherein the method may include forming a plurality of groups of nanotubes over a substrate,...
US20150294871 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE  
According to a first aspect of the present invention, a method of manufacturing semiconductor device includes the step of preparing a silicon substrate. The silicon substrate includes an N-type...
US20140004679 METHOD OF FABRICATING SEMICONDUCTOR DEVICE  
A method for fabricating a semiconductor device includes forming a metal layer over a substrate, forming a capping layer over the metal layer, and densifying the metal layer through a heat treatment.

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