Matches 1 - 13 out of 13
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US20090309227 FABRICATION OF INTERCONNECTS IN LOW-K INTERLAYER DIELECTRICS  
A method for forming deep lithographic interconnects between a first metal and a second metal is provided. The method comprises depositing a first insulator layer on a semiconductor substrate;...
US20090250819 METAL LINE OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME  
The invention relates to a metal line of a semiconductor device and a method of forming the same. According to a method of forming a metal line of a semiconductor device in accordance with an...
US20090061618 Method of Manufacturing Metal Interconnection  
A method of manufacturing a semiconductor is provided. A fist metal layer can be formed on a lower structural layer, and an interlayer metal dielectric (IMD) layer can be formed on the first metal...
US20080299762 Method for forming interconnects for 3-D applications  
A method for forming an interconnect, comprising (a) providing a substrate ( 203 ) with a via ( 205 ) defined therein; (b) forming a seed layer ( 211 ) such that a first portion of the seed layer...
US20080293238 Semiconductor device and method for fabricating the same  
A method for fabricating a semiconductor device is provided. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a first insulating layer, a first...
US20080284039 INTERCONNECT STRUCTURES WITH TERNARY PATTERNED FEATURES GENERATED FROM TWO LITHOGRAPHIC PROCESSES  
A method for fabricating an interconnect structure for interconnecting a semiconductor substrate to have three distinct patterned structures such that the interconnect structure provides both a low...
US20080277787 METHOD AND PAD DESIGN FOR THE REMOVAL OF BARRIER MATERIAL BY ELECTROCHEMICAL MECHANICAL PROCESSING  
A method and apparatus for processing barrier and metals disposed on a substrate in an electrochemical mechanical planarizing system are provided. In certain embodiments a method for...
US20080150142 Multilevel wiring, laminated aluminum wiring, semiconductor device and manufacturing method of the same  
A contact plug is formed in a contact hole which is formed in an interlayer insulation film and then a barrier metal layer and a main wiring layer, which form a wiring layer in all, are formed on...
US20080124913 Slurry compositions and CMP methods using the same  
The exemplary embodiments of the present invention providing new slurry compositions suitable for use in processes involving the chemical mechanical polishing (CMP) of a polysilicon layer. The...
US20080036091 Semiconductor integrated circuit device  
Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a...
US20080032498 METHOD FOR FABRICATING METAL LINE OF SEMICONDUCTOR DEVICE  
Provided is a method for fabricating a metal line of a semiconductor device. In a method according to one embodiment, an interlayer insulating layer is formed on a semiconductor substrate. After...
US20080026583 COMPOSITIONS AND METHODS FOR MODIFYING A SURFACE SUITED FOR SEMICONDUCTOR FABRICATION  
The disclosure pertains to compositions and methods for modifying or refining the surface of a wafer suited for semiconductor fabrication. The compositions include working liquids useful in...
US20080020565 Dual Damascene Copper Process Using a Selected Mask  
A method for creating a dual damascene structure while using only one lithography and masking step. Conventional dual damascene structures utilize two lithography steps: one to mask and expose the...
Matches 1 - 13 out of 13