Matches 1 - 47 out of 47


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US20130178057 Methods of Forming Conductive Structures Using a Dual Metal Hard Mask Technique  
Disclosed herein are various methods of forming conductive structures, such as conductive lines and vias, using a dual metal hard mask integration technique. In one example, the method includes...
US20120319285 INTEGRATED CIRCUITS INCLUDING BARRIER POLISH STOP LAYERS AND METHODS FOR THE MANUFACTURE THEREOF  
Embodiments of a method for fabricating integrated circuits are provided, as are embodiments of an integrated circuit. In one embodiment, the method includes the steps of depositing an interlayer...
US20060001168 Technique for forming a dielectric interlayer above a structure including closely spaced lines  
By depositing the lower portion of a silicon dioxide interlayer dielectric by means of SACVD or HDP-CVD techniques, the generation of voids may be reliably avoided even for devices having spaces...
US20070224806 Metal polishing slurry  
The metal polishing slurry according to the present invention for use in chemical mechanical polishing during semiconductor device fabrication contains at least one compound of formula (A) below...
US20070152252 Reducing aluminum dissolution in high pH solutions  
A method for reducing the dissolution of aluminum gate electrodes in a high pH clean chemistry comprises modifying the high pH clean chemistry to include a silanol-based chemical. The...
US20060172527 Method for forming a defined recess in a damascene structure using a CMP process and a damascene structure  
The present invention provides a technique that enables the formation of a recessed upper surface of an interconnect line to form an inlaid barrier cap layer on top of an inter-connect line to...
US20080020565 Dual Damascene Copper Process Using a Selected Mask  
A method for creating a dual damascene structure while using only one lithography and masking step. Conventional dual damascene structures utilize two lithography steps: one to mask and expose the...
US20050176241 Method of forming metal wiring of semiconductor devices  
Disclosed herein is a method of forming metal wirings of semiconductor devices a lower metal wiring is formed in a dual damascene pattern formed in an interlayer insulating film and is etched as...
US20050059235 Method for improving oxide layer flatness  
A method for improving the flatness of an oxide layer comprising the steps of providing a semiconductor structure, forming a polysilicon layer on the semiconductor structure, utilizing chemical...
US20070004209 Slurry for chemical mechanical polishing of aluminum  
Described herein are embodiments of a slurry used for the chemical mechanical polishing a substrate that includes aluminum or an aluminum alloy features having a width of less than 1 um. The...
US20060134908 Polishing method  
A method for polishing an object to form wiring for a semiconductor device includes: removing part of an outside portion of a conductor layer through chemical and mechanical polishing to expose an...
US20140353845 SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR  
A production method for a semiconductor device having a multi-level interconnection structure including a plurality of interconnection layers stacked one on another on a semiconductor substrate is...
US20080150142 Multilevel wiring, laminated aluminum wiring, semiconductor device and manufacturing method of the same  
A contact plug is formed in a contact hole which is formed in an interlayer insulation film and then a barrier metal layer and a main wiring layer, which form a wiring layer in all, are formed on...
US20050084990 Endpoint detection in manufacturing semiconductor device  
A method of manufacturing a semiconductor device that comprises the steps of providing a semiconductor wafer including a patterned layer, forming a first insulating layer over the patterned layer...
US20070298606 CHEMICAL-MECHANICAL POLISHING METHOD AND APPARATUS  
A method for manufacturing a semiconductor multilayer wafer by manufacturing an intermediate multilayer wafer having a polished layer from which a surface layer is obtained. The surface roughness...
US20120115303 METHOD OF FABRICATING DAMASCENE STRUCTURES  
Method of forming wires in integrated circuits. The methods include forming a wire in a first dielectric layer on a substrate; forming a dielectric barrier layer over the wire and the first...
US20070155168 METHOD FOR FORMING A CONDUCTIVE PLUG OF A SEMICONDUCTOR DEVICE  
Embodiments relate to a method for forming a conductive plug of a semiconductor device that may include preparing a semiconductor substrate having multilayer metal interconnections, forming...
US20100120242 METHOD TO PREVENT LOCALIZED ELECTRICAL OPEN CU LEADS IN VLSI CU INTERCONNECTS  
One embodiment of the present invention relates a method for preventing the formation of electrical opens due to localized copper dissolution during fabrication of metal interconnect wires. More...
US20120086101 INTEGRATED CIRCUIT AND INTERCONNECT, AND METHOD OF FABRICATING SAME  
The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC includes at least one...
US20060211157 Novel CMP endpoint detection process  
The present invention provides a method for polishing a layer of material, a method for manufacturing a damascene interconnect structure, and a method for manufacturing an integrated circuit. The...
US20050059233 Process for forming metal damascene structure to prevent dielectric layer peeling  
A process for forming a metal damascene structure. First, a cap layer is formed on a first metal layer, and a dielectric layer is formed on the cap layer. Next, the dielectric layer is etched to...
US20050170638 Method for forming dual damascene interconnect structure  
A method for forming dual damascene structures within a semiconductor device utilizes a plug material that is soluble in alkaline developers such as 2.38 wt % TMAH. The plug material is introduced...
US20050170641 Multilayered wiring structure, method of forming buried wiring, semiconductor device, method of manufacturing semiconductor device, semiconductor mounted device, and method of manufacturing semiconductor mounted device  
A method of forming a buried wiring in a low-k dielectric film, includes: forming a low-k dielectric film having a dielectric constant of 3 or less on an underlayer; removing the low-k dielectric...
US20060024954 Copper damascene barrier and capping layer  
A method for forming a damascene with improved electrical properties and resulting structure thereof including providing at least one dielectric insulating layer overlying a first etch stop layer;...
US20150054136 METHOD OF PROVIDING A VIA HOLE AND ROUTING STRUCTURE  
A method of providing a via hole and routing structure includes: providing a substrate wafer having recesses and blind holes provided in the surface of the wafer; providing an insulating layer in...
US20080277787 METHOD AND PAD DESIGN FOR THE REMOVAL OF BARRIER MATERIAL BY ELECTROCHEMICAL MECHANICAL PROCESSING  
A method and apparatus for processing barrier and metals disposed on a substrate in an electrochemical mechanical planarizing system are provided. In certain embodiments a method for...
US20050048783 Method for planarizing a surface of a semiconductor wafer  
In a method for polishing a surface of a semiconductor wafer, a first polishing process using slurry is performed on a surface of the insulator layer after an insulator layer is deposited on the...
US20090061618 Method of Manufacturing Metal Interconnection  
A method of manufacturing a semiconductor is provided. A fist metal layer can be formed on a lower structural layer, and an interlayer metal dielectric (IMD) layer can be formed on the first metal...
US20070173056 Semiconductor device fabrication method and polishing apparatus  
A method for fabricating a semiconductor device includes forming a barrier metal film on a substrate with an opening defined therein, forming a copper-containing film on said barrier metal film...
US20080026583 COMPOSITIONS AND METHODS FOR MODIFYING A SURFACE SUITED FOR SEMICONDUCTOR FABRICATION  
The disclosure pertains to compositions and methods for modifying or refining the surface of a wafer suited for semiconductor fabrication. The compositions include working liquids useful in...
US20110003471 Fabrication of interconnects in a low-k interlayer dielectrics  
A method for forming deep lithographic interconnects between a first metal and a second metal is provided. The method comprises depositing a first insulator layer on a semiconductor substrate;...
US20070190777 METHOD OF MAKING DENSE, CONFORMAL, ULTRA-THIN CAP LAYERS FOR NANOPOROUS LOW-K ILD BY PLASMA ASSISTED ATOMIC LAYER DEPOSITION  
Barrier layers and methods for forming barrier layers on a porous layer are provided. The methods can include chemically adsorbing a plurality of first molecules on a surface of the porous layer...
US20050090094 Method of forming a metal pattern for a semiconductor device  
A method of forming a conductive pattern includes preparing a semiconductor substrate having a conductive pattern, forming an interlayer dielectric pattern having an opening exposing the...
US20050079703 Method for planarizing an interconnect structure  
A method of forming an interconnect structure (e.g., copper interconnect structure, and the like) on a semiconductor substrate. The interconnect structure is formed by depositing within trenches...
US20130012019 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE  
A method for fabricating a semiconductor device includes (a) depositing an insulating film on a semiconductor substrate; (b) forming a recess in the insulating film; (c) depositing a conductive...
US20090309227 FABRICATION OF INTERCONNECTS IN LOW-K INTERLAYER DIELECTRICS  
A method for forming deep lithographic interconnects between a first metal and a second metal is provided. The method comprises depositing a first insulator layer on a semiconductor substrate;...
US20080299762 Method for forming interconnects for 3-D applications  
A method for forming an interconnect, comprising (a) providing a substrate (203) with a via (205) defined therein; (b) forming a seed layer (211) such that a first portion of the seed layer...
US20070072425 Substrate and method for producing same  
A substrate according to the present invention includes a metal plate, and an insulating film, which is provided on the surface of the metal plate and which includes needle alumina particles and...
US20050260855 Method and apparatus for planarizing a semiconductor wafer  
A method for planarizing a semiconductor wafer includes providing a fluid on a surface of the wafer, the fluid containing particles, and generating a field to apply a force to the particles, the...
US20050130408 Method for forming metal wiring of semiconductor device  
Disclosed is a method for forming a metal wiring of a semiconductor device. After an oxide interlayer is formed on a lower layer including a metal layer pattern, a contact hole exposing an upper...
US20170110369 ELECTRONIC DEVICE AND METHOD FOR PRODUCING SAME  
An electronic device includes: a first insulating film; an interconnection trench on a surface of the first insulating film; an interconnection pattern composed of Cu, the interconnection trench...
US20170062269 SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND STORAGE MEDIUM  
A method of manufacturing a semiconductor device includes preparing a substrate having an interlayer insulating film and a hard mask provided on the interlayer insulating film and having a...
US20160204022 SEMICONDUCTOR DEVICE STRUCTURES WITH IMPROVED PLANARIZATION UNIFORMITY, AND RELATED METHODS  
Semiconductor devices and structures, such as phase change memory devices, include peripheral conductive pads coupled to peripheral conductive contacts in a peripheral region. An array region may...
US20160190005 PHYSICAL UNCLONABLE INTERCONNECT FUNCTION ARRAY  
A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive...
US20150270176 METHODS OF FORMING REDUCED RESISTANCE LOCAL INTERCONNECT STRUCTURES AND THE RESULTING DEVICES  
A method includes forming a layer of insulating material above first and second transistors, within the layer of insulating material, forming a set of initial device-level contacts for each of the...
US20150262867 FORMING ARRAY CONTACTS IN SEMICONDUCTOR MEMORIES  
Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example,...
US20140217598 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME  
According to one embodiment, a semiconductor memory device includes a plurality of interconnects of an nth layer, a plurality of interconnects of a (n+1)th layer, a plurality of stacked films of...

Matches 1 - 47 out of 47