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US20090298279 |
METHOD FOR REDUCING METAL IRREGULARITIES IN ADVANCED METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES
In a manufacturing sequence for forming metallization levels of semiconductor devices, out-gassing of volatile components after an etch process may be initiated immediately after the etch process,...
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US20090294986 |
Methods of Forming Conductive Features and Structures Thereof
Methods of forming features and structures thereof are disclosed. In one embodiment, a method of forming a feature includes forming a first material over a workpiece, forming a first pattern for a...
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US20090294973 |
INTERCONNECT STRUCTURE FOR INTEGRATED CIRCUITS HAVING IMPROVED ELECTROMIGRATION CHARACTERISTICS
An interconnect structure for an integrated circuit (IC) device includes an elongated, electrically conductive line comprising one or more segments formed at a first width, w 1 , and one or more...
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US20090294953 |
INTEGRATED CIRCUIT PACKAGE MODULE AND METHOD OF THE SAME
The present invention discloses an integrated circuit module and method of manufacturing the same. The integrated circuit module includes a chip and a carrier supporting the chip. The carrier...
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US20090289368 |
INTERCONNECT STRUCTURE HAVING ENHANCED ELECTROMIGRATION RELIABILTY AND A METHOD OF FABRICATING SAME
An interconnect structure having improved electromigration (EM) reliability is provided. The inventive interconnect structure avoids a circuit dead opening that is caused by EM failure by...
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US20090289324 |
MASK OVERHANG REDUCTION OR ELIMINATION AFTER SUBSTRATE ETCH
A method of forming IC devices includes providing a substrate and forming a patterned masking layer including at least one masked region having at least one masking layer, and a feature region...
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US20090286392 |
MANUFACTURING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
A Cu-CMP step applied to processes for 130 nm, 90 nm, and 65 nm technical nodes or the like mainly employs slurry to which an anticorrosive agent is added for preventing corrosion of Cu wiring. The...
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US20090286391 |
SEMICONDUCTOR DEVICE FABRICATION METHOD
According to one aspect of the invention, there is provided a qsemiconductor device fabrication method having: forming a film on a semiconductor substrate; forming a mask comprising a...
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US20090280637 |
Method of manufacturing semiconductor device including ultra low dielectric constant layer
Provided is a method of manufacturing a semiconductor device. The method employs multi-step removal on a plurality of different porogens included in a low dielectric layer both before and after...
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US20090280636 |
METHODS OF FABRICATING INTERCONNECT STRUCTURES CONTAINING VARIOUS CAPPING MATERIALS FOR ELECTRICAL FUSE AND OTHER RELATED APPLICATIONS
Methods are provided for fabricating interconnect structures containing various capping materials for electrical fuses and other related applications. The method includes forming a first...
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US20090275193 |
METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third...
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US20090275180 |
METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
A conventional power MOSFET structure is difficult to improve a breakdown voltage of an element even using a super-junction structure. A power MOSFET according to an embodiment of the invention is...
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US20090275176 |
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
A semiconductor device and method of fabricating the same, which forms a contact hole, a via hole or a via contact hole with multiple profiles with various taper angles. The semiconductor device...
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US20090273083 |
ELECTRICALLY CONDUCTIVE FLUID INTERCONNECTS FOR INTEGRATED CIRCUIT DEVICES
Disclosed are embodiments of an electrically conductive fluid interconnect for coupling an integrated circuit (IC) device to a substrate. The IC device may be coupled to the substrate in a...
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US20090269920 |
METHOD OF FORMING INTERCONNECTION LINE AND METHOD OF MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE
A method of forming an interconnection line and a method of manufacturing a thin film transistor substrate are provided in accordance with one or more embodiments of the present invention. The...
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US20090267216 |
INKJET PRINTED LEADFRAMES
Apparatuses and methods for inkjet printing electrical interconnect patterns such as leadframes for integrated circuit devices are disclosed. An apparatus for packaging includes a thin substrate...
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US20090258487 |
Method for Improving the Reliability of Low-k Dielectric Materials
A method for forming an integrated circuit structure includes providing a semiconductor substrate; forming a low-k dielectric layer over the semiconductor substrate; generating hydrogen radicals...
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US20090243112 |
Copper interconnection structure, semiconductor device, and method for forming copper interconnection structure
A copper interconnection structure includes an insulating layer, an interconnection and a barrier layer. The insulating layer includes silicon (element symbol: Si), carbon (element symbol: C),...
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US20090239377 |
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device includes a semiconductor substrate, a copper-containing metal interconnect over the semiconductor substrate, and a copper-containing connection plug, and the metal...
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US20090239373 |
CHEMICAL MECHANICAL POLISHING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A chemical mechanical polishing method comprises polishing an organic film using a slurry including polymer particles having a surface functional group and a water-soluble polymer.
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US20090239372 |
Seed Layers for Electroplated Interconnects
One embodiment of the present invention is a method for depositing two or more seed layers for electroplating metallic interconnects over a substrate, the substrate having a patterned insulating...
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US20090233437 |
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURED THEREBY
A method of manufacturing a semiconductor device and a semiconductor device manufactured thereby are provided. The method includes forming a molding layer on a substrate, forming support patterns...
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US20090218699 |
METAL INTERCONNECTS IN A DIELECTRIC MATERIAL
A semiconductor device includes an interconnect having electrically conductive portions and a dielectric layer made of a first dielectric material. A trench is formed in the dielectric layer. The...
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US20090218690 |
Reduced-Stress Through-Chip Feature and Method of Making the Same
A feature is inscribed in a major surface of a microelectronic workpiece having a material property expressed as a reference coefficient value. The feature includes a first material having a first...
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US20090215261 |
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device having a through electrode excellent in performance as for an electrode and manufacturing stability is provided. There is provided a through electrode composed of a...
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US20090212439 |
FLUORINE DEPLETED ADHESION LAYER FOR METAL INTERCONNECT STRUCTURE
A line trough and a via cavity are formed within a dielectric layer comprising a fluorosilicate glass (FSG) layer. A fluorine depleted adhesion layer is formed within the line trough and the via...
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US20090212431 |
THERMALLY PROGRAMMABLE ANTI-REVERSE ENGINEERING INTERCONNECTS AND METHODS OF FABRICATING SAME
An interconnect and method of making the interconnect. The method includes forming a dielectric layer on a substrate, the dielectric layer having a top surface and a bottom surface; forming a first...
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US20090203208 |
COPPER ALLOY FOR WIRING, SEMICONDUCTOR DEVICE, METHOD FOR FORMING WIRING, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A wiring metal contains a polycrystal of copper (Cu) as a primary element and an additional element other than Cu, and concentration of the additional element is, at crystal grain boundaries...
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US20090200583 |
Feature Patterning Methods
Methods of patterning features of semiconductor devices and methods of processing and fabricating semiconductor devices are disclosed. In one embodiment, a method of processing a semiconductor...
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US20090197386 |
Methods Of Forming An Interconnect Between A Substrate Bit Line Contact And A Bit Line In DRAM, And Methods Of Forming DRAM Memory Cells
The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit...
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US20090189287 |
NOBLE METAL CAP FOR INTERCONNECT STRUCTURES
An interconnect structure that includes a dielectric material having a dielectric constant of about 3.0 or less is provided. This low k dielectric material has at least one conductive material...
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US20090186477 |
METHOD OF FORMING METAL WIRING OF NONVOLATILE MEMORY DEVICE
A method of forming metal wirings of a nonvolatile memory device include forming a first insulating layer over a semiconductor substrate including a first junction area and a second junction area,...
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US20090186476 |
STRUCTURE AND METHOD FOR IMPROVED SRAM INTERCONNECT
A method of forming an improved static random access memory (SRAM) interconnect structure is provided. The method includes forming a sidewall spacer around a periphery of a patterned poly-silicon...
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US20090184429 |
Integrated Circuit Comprising Conductive Lines and Contact Structures and Method of Manufacturing an Integrated Circuit
An integrated circuit comprises a first conductive lines and second lines as well as contact structures being in contact with the first and second conductive lines. The first conductive lines are...
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US20090181534 |
CHARGING-FREE ELECTRON BEAM CURE OF DIELECTRIC MATERIAL
An ultra low-k dielectric material layer is formed on a semiconductor substrate. In one embodiment, a grid of wires is placed at a distance above a top surface of the ultra low-k dielectric...
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US20090174067 |
AIRGAP-CONTAINING INTERCONNECT STRUCTURE WITH PATTERNABLE LOW-K MATERIAL AND METHOD OF FABRICATING
The present invention provides a method of fabricating an airgap-containing interconnect structure in which a patternable low-k material replaces the need for utilizing a separate photoresist and a...
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US20090173993 |
Structure and Method of Forming a Topside Contact to a Backside Terminal of a Semiconductor Device
A vertically conducting semiconductor device includes a semiconductor substrate having a topside surface and a backside surface. The semiconductor substrate serves as a terminal of the vertically...
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US20090170307 |
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A metal layer is formed on an upper surface of a resin layer provided to cover a plurality of semiconductor chips at a side on which an internal connecting terminal is disposed and the internal...
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US20090170306 |
PROCESS FOR FILLING RECESSED FEATURES IN A DIELECTRIC SUBSTRATE
A process for filling recessed features of a dielectric substrate for a semiconductor device, comprises the steps (a) providing a dielectric substrate having a recessed feature in a surface...
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US20090170305 |
METHOD FOR IMPROVING ELECTROMIGRATION LIFETIME FOR CU INTERCONNECT SYSTEMS
A method for forming a single damascene and/or dual damascene interconnect structure, comprising: performing front end processing, depositing copper, annealing the copper, performing CMP...
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US20090166867 |
METAL INTERCONNECT STRUCTURES FOR SEMICONDUCTOR DEVICES
Cu interconnect structures using a bottomless liner to reduce the copper interfacial electron scattering and lower the electrical resistance are described in this application. The interconnect...
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US20090160051 |
Semiconductor Chip, Method of Fabricating the Same and Semiconductor Chip Stack Package
Provided are a semiconductor chip, a method of fabricating a semiconductor chip, and a semiconductor chip stack package. The semiconductor chip includes a semiconductor substrate and a...
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US20090155995 |
Self-aligned contact formation utilizing sacrificial polysilicon
In general, in one aspect, a method includes forming a spacer layer over a substrate having patterned stacks formed therein and trenches between the patterned stacks. A sacrificial polysilicon...
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US20090155994 |
FORMING THIN FILM TRANSISTORS USING ABLATIVE FILMS WITH PRE-PATTERNED CONDUCTORS
An ablative film comprising a substrate; at least one ablative layer that is removable by exposure to radiation; one or more deposited conductors; and an active layer including a semiconductor...
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US20090152641 |
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING
A semiconductor memory device includes: a first n-type transistor; a first p-type transistor; a first wiring layer having a first interconnecting portion for connecting a drain of the first n-type...
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US20090149017 |
METHOD OF CLEANING SEMICONDUCTOR SUBSTRATE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SUBSTRATE PROCESSING APPARATUS FOR USE IN THE SAME
A semiconductor substrate processing apparatus is provided with a cleaning process chamber containing a semiconductor substrate for performing a cleaning process on the semiconductor substrate....
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US20090146193 |
Conductive Interconnects
A method of making a conductive interconnect structure includes the steps of: electrodepositing a metal on a conductive surface ( 4 ) of a carrier ( 2 ) to form a first elongate conductive...
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US20090140433 |
MEMS chip-to-chip interconnects
A chip-to-chip interconnect system suited for MEMS that do not require low-resistance connections is described. The interconnects may be fabricated simultaneously with MEMS ribbon structures such...
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US20090137111 |
METHOD OF FABRICATING METAL INTERCONNECTION AND METHOD OF FABRICATING IMAGE SENSOR USING THE SAME
A method of fabricating a metal interconnection and a method of fabricating image sensor using the same are provided. The method of fabricating a metal interconnection including forming a...
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US20090134517 |
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A first insulating film is formed on a semiconductor substrate. A first interconnection is formed in a trench formed in the first insulating film. A first barrier film is formed between the first...
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