Sign up
Matches 1 - 46 out of 46

AcclaimIP-ad

Match Document Document Title
US20130328205 INTEGRATED CIRCUITS HAVING A CONTINUOUS ACTIVE AREA AND METHODS FOR FABRICATING SAME  
Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes a standard cell having a first boundary, a second boundary...
US20120049320 ELECTRONIC DEVICE INCLUDING A FEATURE IN A TRENCH  
A semiconductor substrate can be patterned to define a trench and a feature. In an embodiment, the trench can be formed such that after filling the trench with a material, a bottom portion of the...
US20090212424 ROUTING STRUCTURE OF RE-DISTRIBUTION LAYER AND METHOD FOR RE-DISTRIBUTING ROUTING STRUCTURE IN INTEGRATED CIRCUIT  
A routing structure of an RDL of a chip is provided. The routing structure comprises a power route, a plurality of first stripes, a ground route, and a plurality of second stripes. The power route...
US20090128188 Pad invariant FPGA and ASIC devices  
A three dimensional semiconductor device, comprising: a plurality of circuit blocks including programmable logic blocks having predetermined positions within the device; a plurality of pads having...
US20120097208 METHOD FOR THE PRODUCTION AND SERIES CONNECTION OF STRIP-SHAPED ELEMENTS ON A SUBSTRATE  
Provided is a method for generating, and for connecting in series, stripe-shaped elements, wherein less space is required for the series connection as compared to the prior art.
US20080121709 Semiconductor Chip With Identification Codes, Manufacturing Method Of The Chip And Semiconductor Chip Management System  
There is provided a semiconductor chip using an electrical identification code and an optical identification code, both of the codes being formed in the same process to be always in one-to-one...
US20130257478 PERMUTABLE SWITCHING NETWORK WITH ENHANCED INTERCONNECTIVITY FOR MULTICASTING SIGNALS  
In one embodiment, the integrated circuit has a L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors. The integrated circuit can be used in electronic...
US20120105104 PERMUTABLE SWITCHING NETWORK WITH ENHANCED INTERCONNECTIVITY FOR MULTICASTING SIGNALS  
In one embodiment, the integrated circuit has a L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors. The integrated circuit can be used in electronic...
US20080116578 Initiation layer for reducing stress transition due to curing  
An integrated circuit includes an etch stop layer over a substrate; a UV blocker layer on the etch stop layer, wherein the UV blocker layer has a high extinction coefficient; and a low-k dielectric...
US20080111244 COPPER-METALLIZED INTEGRATED CIRCUITS HAVING AN OVERCOAT FOR PROTECTING BONDABLE METAL CONTACTS AND IMPROVING MOLD COMPOUND ADHESION  
A semiconductor device having copper interconnecting metallization (111) protected by a first (102) and a second (120) overcoat layer (homogeneous silicon dioxide), portions of the metallization...
US20080309314 Voltage regulator and method of manufacturing the same  
A voltage regulator and a method of manufacturing the voltage regulator, which can provide a desired output voltage of the voltage regulator using a plurality of metal wires, arranged in regular...
US20100197117 MIXED-SCALE ELECTRONIC INTERFACES  
Certain embodiments of the present invention are directed to a method of programming nanowire-to-conductive element electrical connections. The method comprises: providing a substrate including a...
US20120009774 DEVICE FOR DETECTING AN ATTACK AGAINST AN INTEGRATED CIRCUIT  
An integrated circuit including an intrusion attack detection device. The device includes a single-piece formed of a conductive material and surrounded with an insulating material and includes at...
US20120194217 INPUT/OUTPUT CORE DESIGN AND METHOD OF MANUFACTURE THEREFOR  
One aspect provides an input/output cell. The input/output cell, in one example, includes an input/output layout boundary delineated on a substrate, wherein the input/output layout boundary defines...
US20120119785 INPUT/OUTPUT CORE DESIGN AND METHOD OF MANUFACTURE THEREFOR  
One aspect provides an input/output cell. The input/output cell, in one example, includes an input/output layout boundary delineated on a substrate, wherein the input/output layout boundary defines...
US20140312504 INTERCONNECT LINE SELECTIVELY ISOLATED FROM AN UNDERLYING CONTACT PLUG  
A means for selectively electrically connecting an electrical interconnect line, such as a bit line of a memory cell, with an associated contact stud and electrically isolating the interconnect...
US20120156870 Chip Pad Resistant to Antenna Effect and Method  
A chip pad structure of an integrated circuit (IC) and the method of forming are disclosed. The chip pad comprises a main pad portion and a ring pad portion. During a charging process involved in...
US20090321871 Chip Pad Resistant to Antenna Effect and Method  
A chip pad structure of an integrated circuit (IC) and the method of forming are disclosed. The chip pad comprises a main pad portion and a ring pad portion. During a charging process involved in...
US20100044858 Product Chips and Die With a Feature Pattern That Contains Information Relating to the Product Chip, Methods for Fabricating Such Product Chips and Die, and Methods for Reading a Feature Pattern From a Packaged Die  
Product chips and die, methods for fabricating product chips, and methods for tracking the identity of die after singulation from a wafer. The product chips and die include a pattern of features...
US20100006912 Planar Metal-Insulator-Metal Circuit Element and Method for Planar Integration of Same  
A complementary metal-oxide-semiconductor (CMOS) static random-access-memory (SRAM) element comprising a planar metal-insulator-metal (MIM) capacitor is disclosed, and the planar MIM capacitor is...
US20100006904 Apparatus and Method for Input/Output Module That Optimizes Frequency Performance in a Circuit  
A circuit can include a module having signal pads that are configurable to route signals between the circuit and at least one external device. The module can also have unused pads that are...
US20110058292 Integrated RF ESD Protection for High Frequency Circuits  
The invention relates to a high-frequency integrated circuit requiring ESD protection for a circuit node. One or more metallic layer is deposited within the integrated circuit and patterned to form...
US20140015143 METHODS OF FORMING NANO-SCALE PORES, NANO-SCALE ELECTRICAL CONTACTS, AND MEMORY DEVICES INCLUDING NANO-SCALE ELECTRICAL CONTACTS, AND RELATED STRUCTURES AND DEVICES  
Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of...
US20080073789 Method Of Identifying And/Or Programming An Integrated Circuit  
A chip and a method of fabricating the chip for low cost chip identification circuitry. In one embodiment, a method of manufacturing an integrated circuit includes formation of a multi-level...
US20080128710 Producing SiC Packs on a Wafer Plane  
A method for producing at least one semiconductor component group, in particular a SiC semiconductor component group, includes the step of producing a number of semiconductor components on a...
US20110263116 ULTRAHIGH DENSITY PATTERNING OF CONDUCTING MEDIA  
A reconfigurable device and a method of creating, erasing, or reconfiguring the device are provided. At an interface between a first insulating layer and a second insulating layer, an electrically...
US20090166758 INTEGRATED CIRCUIT STRUCTURE WITH ELECTRICAL STRAP  
A method of forming an IC is presented. The method includes providing a substrate having a plurality of transistors formed thereon. The transistors have gate stack, source and drain regions. An...
US20070224798 Semiconductor device and medium of fabricating the same  
A highly-reliable semiconductor device and a method of fabricating the semiconductor device, while stably carrying out IC test, are proposed. A pad portion after an IC test using a probe is covered...
US20110261491 MONITOR CIRCUIT FOR DETERMINING THE LIFETIME OF A SEMICONDUCTOR DEVICE  
A circuit comprises a first conductor, a second conductor, and a first detect and disconnect circuit. The first conductor is coupled to a first power supply voltage terminal. The second conductor...
US20090020856 SEMICONDUCTOR DEVICE STRUCTURES AND METHODS FOR SHIELDING A BOND PAD FROM ELECTRICAL NOISE  
Semiconductor device structures and methods for shielding a bond pad from electrical noise generated by active circuitry of an integrated circuit carried on a substrate. The structure includes...
US20060223313 Copper interconnect post for connecting a semiconductor chip to a substrate and method of fabricating the same  
A semiconductor chip comprising at least one contact area for electrically connecting the chip to a substrate, the contact area comprising a metallic contact pad covered by a seed layer and at...
US20080217751 SUBSTRATE FOR MOUNTING SEMICONDUCTOR ELEMENT AND METHOD OF MANUFACTURING THE SAME  
The present invention provides a semiconductor element mounting substrate 101 including: a base substrate 1 having a region 2 for mounting a semiconductor element 11, the region 2 being set on the...
US20100060559 DISPLAY DEVICE, LIQUID CRYSTAL DISPLAY DEVICE, AND METHOD FOR MANUFACTURING DISPLAY DEVICE  
A display device displays images with a plurality of signal lines and includes spare lines, each being arranged to be connectable to the signal lines so as to be used for recovery of the signal...
US20080296668 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE  
A semiconductor device has a substrate having a plurality of neighboring trenches, and a contact area, one mesa stripe each being formed between two neighboring trenches. The contact area contacts...
US20070241446 Two-sided wafer escape package  
A method and structure provides a Direct Write Wafer Level Chip Scale Package (DWWLCSP) that utilizes permanent layers/coatings and direct write techniques to pattern these layers/coatings, thereby...
US20080284029 Contact structures and semiconductor devices including the same and methods of forming the same  
Methods of forming a contact structure in a semiconductor device include providing a semiconductor substrate including active regions and word lines crossing the active regions. A first interlayer...
US20080157366 SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF  
A semiconductor device and fabricating method thereof are disclosed. Embodiments relate to forming metal lines having a prescribed pattern over a lower insulating interlayer, forming a silicon...
US20140248764 METHODS OF FORMING STRUCTURES ON AN INTEGRATED CIRCUIT PRODUCT  
One illustrative method disclosed herein includes forming a seed layer above a substrate that includes a conductive region, wherein the seed layer is comprised of a metal-containing material,...
US20130059436 DEVICE FABRICATION  
Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device...
US20100159688 Device fabrication  
Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device...
US20090230542 Semiconductor Device With Integrated Passive Circuit and Method of Making the Same Using Sacrificial Substrate  
A semiconductor device is made by providing a sacrificial substrate, forming a first insulating layer over the sacrificial substrate, forming a first passivation layer over the first insulating...
US20090142916 APPARATUS AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT  
On aspect is a method to manufacture an integrated circuit including a reshaping process of the wafer edge region and an apparatus to perform the reshaping process.
US20080203545 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION THEREOF  
A ground line is exposed by removing a surface protecting film, which covers an uppermost metal wiring layer, and providing an opening portion at a portion of a top surface of a semiconductor chip,...
US20140024146 SEMICONDUCTOR STRUCTURE  
A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit...
US20130059419 METHODS OF FORMING SEMICONDUCTOR DEVICE PACKAGES INCLUDING A SEMICONDUCTOR DEVICE AND A REDISTRIBUTION ELEMENT, METHODS OF FORMING REDISTRIBUTION ELEMENTS AND METHODS FOR PACKAGING SEMICONDUCTOR DEVICES  
A method for fabricating a chip-scale board-on-chip substrate, or redistribution element, includes forming conductive planes on opposite sides of a substrate. A first of the conductive planes...
US20120302054 CONDUCTIVE STRUCTURES FOR MICROFEATURE DEVICES AND METHODS FOR FABRICATING MICROFEATURE DEVICES  
Methods for fabricating conductive structures on and/or in interposing devices and microfeature devices that are formed using such methods are disclosed herein. In one embodiment, a method for...
Matches 1 - 46 out of 46