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US20130321962 ESD-ROBUST I/O DRIVER CIRCUITS  
An ESD-robust I/O driver circuit is disclosed. Embodiments include providing a first NMOS transistor having a first source, a first drain, and a first gate; coupling the first source is coupled to...
US20110117723 NANO IMPRINT TECHNIQUE WITH INCREASED FLEXIBILITY WITH RESPECT TO ALIGNMENT AND FEATURE SHAPING  
By forming metallization structures on the basis of an imprint technique, in which via openings and trenches may be commonly formed, a significant reduction of process complexity may be achieved...
US20130095649 Chemical Bath Replenishment  
Ions depleted from a chemical bath by a reaction such as plating are continually replenished by production and moving of ions through selectively permeable membranes while isolating potential...
US20120094478 RESIST FEATURE AND REMOVABLE SPACER PITCH DOUBLING PATTERNING METHOD FOR PILLAR STRUCTURES  
A method of making a semiconductor device includes forming a layer over a substrate, forming a plurality of spaced apart features of imagable material over the layer, forming sidewall spacers on...
US20080020559 PAD STRUCTURE DESIGN WITH REDUCED DENSITY  
An interconnect structure includes at least a first interconnect layer and a second interconnect layer. Each of the first and second interconnect layers has a pad structure and each pad structure...
US20130292773 CROSS-COUPLING-BASED DESIGN USING DIFFUSION CONTACT STRUCTURES  
An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a...
US20130295764 METHOD FOR REDUCING DIELECTRIC OVERETCH WHEN MAKING CONTACT TO CONDUCTIVE FEATURES  
A method is provided that includes forming conductive or semiconductive features above a first dielectric material, depositing a second dielectric material above the conductive or semiconductive...
US20120205793 SEED LAYER PASSIVATION  
A method of processing a microfeature workpiece generally includes depositing a first conducting layer, at least partially reducing oxides on the first conducting layer to provide a reduced first...
US20080194094 Tungsten-doped indium oxide structures and methods  
Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain tungsten and monolayers that contain indium are deposited onto a substrate...
US20060099786 Copper interconnect structure with modulated topography and method for forming the same  
A copper interconnect structure used in semiconductor devices includes surfaces having a surface roughness greater than 20 angstroms and which may be greater than 100 angstroms. The conformal...
US20090273001 WIRE BONDING TO CONNECT ELECTRODES  
A light emitting apparatus includes a semiconductor layer having an electrode with two traces physically separated from one another. The light emitting apparatus further includes a wire bond...
US20140203427 LOW ALPHA PARTICLE EMISSION ELECTRICALLY-CONDUCTIVE COATING  
An electrically conductive paste providing low alpha particle emission is provided. A resin and conductive particles are mixed, and a curing agent is added. A solvent is subsequently added. The...
US20140264890 NOVEL PILLAR STRUCTURE FOR USE IN PACKAGING INTEGRATED CIRCUIT PRODUCTS AND METHODS OF MAKING SUCH A PILLAR STRUCTURE  
One illustrative pillar disclosed herein includes a bond pad conductively coupled to an integrated circuit and a pillar comprising a base that is conductively coupled to the bond pad, wherein the...
US20070048991 Copper interconnect structures and fabrication method thereof  
Copper interconnect structures for interconnection. The interconnect structure has a copper recess in a damascene structure with copper filled in a via/trench of a dielectric layer. Furthermore,...
US20130119382 Plating Process and Structure  
A system and method for plating a contact is provided. An embodiment comprises forming protective layers over a contact and a test pad, and then selectively removing the protective layer over the...
US20070281219 Masking techniques and contact imprint reticles for dense semiconductor fabrication  
A reticle comprising isolated pillars is configured for use in imprint lithography. In some embodiments, on a first substrate a pattern of pillars pitch-multiplied in two dimensions is formed in an...
US20080085594 Silver-containing nanoparticles with replacement stabilizer  
A process including: providing a composition comprising silver-containing nanoparticles and molecules of an initial stabilizer on the surface of the silver-containing nanoparticles; and mixing a...
US20080014732 Application of PVD W/WN bilayer barrier to aluminum bondpad in wire bonding  
An aluminum bondpad and method for making the aluminum bondpad is disclosed. In forming aluminum bondpads, a barrier layer is necessary between a copper interconnect layer and the aluminum bondpad...
US20070224794 Single passivation layer scheme for forming a fuse  
An integrated circuit structure comprising a fuse and a method for forming the same are provided. The integrated circuit structure includes a substrate, an interconnection structure over the...
US20140082954 Multilayered Liquid Capacitive Micro Inclinometer  
The present invention relates to a liquid multilayer capacitive micro inclinometer, comprising at least two pairs of differential electrodes, each pair positioned in a same plane; at least one...
US20080211101 Interlayer wiring of semiconductor device using carbon nanotube and method of manufacturing the same  
Provided is an interlayer wiring structure of a semiconductor device using carbon nanotubes, and a method of manufacturing the interlayer wiring structure. The interlayer wiring structure is a...
US20130040451 METHOD FOR PERMANENT CONNECTION OF TWO METAL SURFACES  
A process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate, wherein a...
US20110136332 METHODS OF FORMING INTEGRATED CIRCUIT DEVICES WITH CRACK-RESISTANT FUSE STRUCTURES  
A fuse base insulating region, for example, an insulating interlayer or a compensation region disposed in an insulating interlayer, is formed on a substrate. An etch stop layer is formed on the...
US20070020904 Selectively filling microelectronic features  
Some embodiments of the present invention include filling features using selective fill techniques.
US20070193354 Capacitive micro-machined ultrasonic transducer for element transducer apertures  
A capacitive micro-machined ultrasonic transducer (CMUT) array includes an improved elementary aperture for imaging operations. The transducer can be of a linear, curved linear, annular, matrix or...
US20050245057 Misalignment-tolerant methods for fabricating multiplexing/demultiplexing architectures  
This disclosure relates to misalignment-tolerant processes for fabricating multiplexing/demultiplexing architectures. One process enables fabricating a multiplexing/demultiplexing architecture at a...
US20110095434 APPARATUS AND METHODS OF FORMING MEMORY LINES AND STRUCTURES USING DOUBLE SIDEWALL PATTERNING FOR FOUR TIMES HALF PITCH RELIEF PATTERNING  
The present invention provides apparatus, methods, and systems for fabricating memory lines and structures using double sidewall patterning for four times half pitch relief patterning. The...
US20100167520 Resist feature and removable spacer pitch doubling patterning method for pillar structures  
A method of making a semiconductor device includes forming at least one layer over a substrate, forming at least two spaced apart features of imagable material over the at least one layer, forming...
US20120108052 ELECTRONIC APPARATUS CONTAINING LANTHANIDE YTTRIUM ALUMINUM OXIDE  
Electronic apparatus and methods of forming the electronic apparatus include a lanthanide yttrium aluminum oxide dielectric film on a substrate for use in a variety of electronic systems. The...
US20140001607 PASSIVATION SCHEME  
An integrated circuit includes a substrate and passivation layers. The passivation layers include a bottom dielectric layer formed over the substrate for passivation, a doped dielectric layer...
US20100314752 FORMING AN ETCHED PLANARISED PHOTONIC CRYSTAL STRUCTURE  
A method of forming a photonic crystal (PhC) structure and a PhC structure formed by such method. The method comprises forming holes in a Si-based host layer; filling the holes with a high-density...
US20080079082 Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer  
A technique for and structures for camouflaging an integrated circuit structure and strengthen its resistance to reverse engineering. A plurality of transistors are formed in a semiconductor...
US20130256890 SHALLOW VIA FORMATION BY OXIDATION  
A method, and an apparatus formed thereby, to construct shallow recessed wells on top of exposed conductive vias on the surface of a semiconductor. The shallow recessed wells are subsequently...
US20070166980 Chemical vapor deposition chamber for depositing titanium silicon nitride films for forming phase change memory devices  
Organometallic precursors may be utilized to form titanium silicon nitride films that act as heaters for phase change memories. By using a combination of TDMAT and TrDMASi, for example in a metal...
US20130187264 LOW OHMIC CONTACTS  
A method for forming a device is disclosed. A substrate with a contact region is provided. Vacancy defects are formed in the substrate. The vacancy defects have a peak concentration at a depth DV....
US20120149189 HYDROGEN PASSIVATION OF INTEGRATED CIRCUITS  
An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated...
US20110079884 Hydrogen Passivation of Integrated Circuits  
An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated...
US20080191196 Nanowire heterostructures  
The present invention generally relates to nanoscale heterostructures and, in some cases, to nanowire heterostructures exhibiting ballistic transport, and/or to metal-semiconductor junctions that...
US20110018062 FABRICATION OF SINGLE OR MULTIPLE GATE FIELD PLATES  
A process for fabricating single or multiple gate field plates using consecutive steps of dielectric material deposition/growth, dielectric material etch and metal evaporation on the surface of a...
US20140312500 COMBINING CUT MASK LITHOGRAPHY AND CONVENTIONAL LITHOGRAPHY TO ACHIEVE SUB-THRESHOLD PATTERN FEATURES  
Features are fabricated on a semiconductor chip. The features are smaller than the threshold of the lithography used to create the chip. A method includes patterning a first portion of a feature...
US20140306331 CHIP AND CHIP ARRANGEMENT  
Various embodiments provide a chip. The chip may include a body having two main surfaces and a plurality of side surfaces; a first power electrode extending over at least one main surface and at...
US20120100709 PLATING APPARATUS AND PLATING METHOD  
A plating apparatus allows a substrate holder to be serviced easily while ensuring easy access to the substrate holder and while a substrate is being processed in the plating apparatus. The plating...
US20130193573 METHODS OF STRESS BALANCING IN GALLIUM ARSENIDE WAFER PROCESSING  
Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a...
US20090039347 PROGRAMMING A MICROCHIP ID REGISTER  
A method is disclosed for programming an ID register of a microchip. The method comprises the step, prior to packaging, of attaching at least one additional ID pin to the die of the microchip. The...
US20120326316 METAL CONTACTS FOR MOLECULAR DEVICE JUNCTIONS AND SURFACE-DIFFUSION-MEDIATED DEPOSITION  
Metal contact formation for molecular device junctions by surface-diffusion-mediated deposition (SDMD) is described. In an example, a method of fabricating a molecular device junction by...
US20130196507 Method Of Depositing Metals Using High Frequency Plasma  
Methods for depositing metal layers, and more specifically TaN layers, using CVD and ALD techniques are provided. In one or more embodiments, the method includes sequentially exposing a substrate...
US20050260847 Method for forming contact window  
A method for forming a contact window is provided. First, a substrate is provided. On the substrate a dielectric layer is formed. Then, the dielectric layer is etched to form an opening, which...
US20120112167 NANOSCALE ELECTRONIC DEVICE  
One example of the present invention is a nanoscale electronic device comprising a first conductive electrode, a second conductive electrode, and an anisotropic dielectric material layered between...
US20100001403 Method for designing semiconductor integrated circuit which includes metallic wiring connected to gate electrode and satisfies antenna criterion  
A method of designing a semiconductor integrated circuit, includes verifying an antenna ratio of a metallic wiring connected to a first gate electrode and the first gate electrode, based on a...
US20090044404 Method for connecting electrodes having apertures  
One embodiment includes a method that includes positioning a first substantially planar electrode including material defining a first aperture into a capacitor stack in alignment with a second...
Matches 1 - 50 out of 330 1 2 3 4 5 6 7 >