Matches 1 - 32 out of 32


Match Document Document Title
US20090294900 Fuse Device  
Implementations are presented herein that relate to a fuse device, an integrated circuit including a fuse device, a method of implementing a fuse device and a method of programming a fuse device.
US20130168841 Programmable Interposer with Conductive Particles  
An exemplary implementation of the present disclosure includes a programmable interposer having top and bottom interface electrodes and conductive particles interspersed within the programmable...
US20110180783 BOUNDARY-MODULATED NANOPARTICLE JUNCTIONS AND A METHOD FOR MANUFACTURE THEREOF  
A method of providing miniaturized size down to nanoscale electronic materials, which may be easily incorporated into the future ever-scaling down power electronics, microelectronics and...
US20110193062 Growth of and Defect Reduction in Nanoscale Materials  
Methods by which the growth of a nanostructure may be precisely controlled by an electrical current are described here. In one embodiment, an interior nanostructure is grown to a predetermined...
US20090179192 Nanowire-Based Semiconductor Device And Method Employing Removal Of Residual Carriers  
A nanowire-based device and method employ removal of residual carriers. The nanowire-based device includes a semiconductor nanowire having a semiconductor junction, and a residual carrier sink....
US20120306048 ELECTRICALLY PROGRAMMABLE METAL FUSE  
A metal electrically programmable fuse (“eFuse”) includes a metal strip, having a strip width, of a metal line adjoined to wide metal line portions, having widths greater than the metal strip...
US20130130474 Quantum Well Device  
An apparatus includes a primary planar quantum well and a planar distribution of dopant atoms. The primary planar quantum well is formed by a lower barrier layer, a central well layer on the lower...
US20100308302 Quantum Well Device  
An apparatus includes a primary planar quantum well and a planar distribution of dopant atoms. The primary planar quantum well is formed by a lower barrier layer, a central well layer on the lower...
US20110254117 Electrical Devices Including Dendritic Metal Electrodes  
The present invention relates generally to electrical devices. The present invention relates more particularly to electrical devices including dendritic metal electrodes. One aspect of the present...
US20120037990 Method and system for pre-migration of metal ions in a semiconductor package  
According to an embodiment of the present disclosure, a method of pre-migrating metal ions is disclosed. A metal in a semiconductor configuration is exposed to water and oxygen to yield metal...
US20140227861 Bottom-Up PEALD Process  
The present disclosure relates to a method and apparatus for performing a plasma enhanced ALD (PEALD) process that provides for improved step coverage. The process introduces a precursor gas into...
US20100193762 NON-VOLATILE MEMORY CELL AND FABRICATION METHOD THEREOF  
A non-volatile memory cell and a fabrication method thereof are provided. The non-volatile memory cell includes an anode; a cathode having a surface facing the anode; a specific structure disposed...
US20110181352 Electrically Actuated Devices  
An electrically actuated device includes a first electrode, a second electrode, and an active region disposed between the first and second electrodes. At least two dopants are present in a...
US20120003818 Field Effect Resistor for ESD Protection  
An electrostatic discharge protection device and methodology are provided for protecting semiconductor devices against electrostatic discharge events by temporarily forming during normal (non-ESD)...
US20110001117 NANOSCALE WIRE-BASED MEMORY DEVICES  
The present invention generally relates to nanotechnology and sub-microelectronic devices that can be used in circuitry, and, in particular, to nanoscale wires and other nanostructures able to...
US20120315740 SELECTIVE DEPOSITION OF POLYMER FILMS ON BARE SILICON INSTEAD OF OXIDE SURFACE  
A method of selective deposition on silicon substrates having regions of bare silicon and regions of oxide formed thereon. The method includes placing the substrate on a wafer support inside a...
US20140159030 PROCESS FOR PREPARING NANOPARTICLE EMBEDDED ELECTRONIC DEVICE  
The present invention relates to a process for preparing an electronic device comprising at least one layer selected from the group consisting of a upper electrode layer, a lower electrode layer,...
US20110186807 Doped graphene electronic materials  
A graphene substrate is doped with one or more functional groups to form an electronic device.
US20110186806 Doped graphene electronic materials  
A graphene substrate is doped with one or more functional groups to form an electronic device.
US20100291757 METHOD OF FORMING, MODIFYING, OR REPAIRING A SEMICONDUCTOR DEVICE USING FIELD-CONTROLLED DIFFUSION  
A technique for altering or repairing the operating state of a semiconductor device comprises field-controlled diffusion of mobile dopant atoms within the metal oxide crystal lattice. When heated...
US20100255615 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE  
A fin-shaped semiconductor region is formed on a substrate, and then the substrate is placed in a chamber. Then, an ignition gas is introduced into a chamber to thereby turn the ignition gas into...
US20100136767 METHOD FOR PRODUCTION OF THIN FILM AND APPARATUS FOR MANUFACTURING THE SAME  
A method for manufacturing a thin film is provided. A substrate is loaded into a chamber. A first reaction gas and a second reaction gas are supplied into the chamber. The first reaction gas is...
US20170096745 DYNAMIC CURRENT DISTRIBUTION CONTROL APPARATUS AND METHOD FOR WAFER ELECTROPLATING  
Methods, systems, and apparatus for plating a metal onto a work piece are described. In one aspect, an apparatus includes a plating chamber, a substrate holder, an anode chamber housing an anode,...
US20160225782 METHODS OF ADJUSTING FLATBAND VOLTAGE OF A MEMORY DEVICE  
Methods for adjusting a flatband voltage of a memory device, including applying a voltage to a control gate of the memory device such that charged species are moved to one of a plurality of...
US20160197151 METHOD TO MAKE BURIED, HIGHLY CONDUCTIVE P-TYPE III-NITRIDE LAYERS  
A conductive, porous gallium-nitride layer can be formed as an active layer in a multilayer structure adjacent to one or more p-type III-nitride layers, which may be buried in a multilayer stack...
US20160042970 PATTERN FORMING METHOD  
A pattern forming method of forming a pattern on an underlying layer of a target object includes forming a block copolymer layer, which includes a first polymer and a second polymer and is...
US20130137242 DYNAMIC CURRENT DISTRIBUTION CONTROL APPARATUS AND METHOD FOR WAFER ELECTROPLATING  
Methods, systems, and apparatus for plating a metal onto a work piece are described. In one aspect, an apparatus includes a plating chamber, a substrate holder, an anode chamber housing an anode,...
US20130052801 METHOD TO ENABLE COMPRESSIVELY STRAINED PFET CHANNEL IN A FINFET STRUCTURE BY IMPLANT AND THERMAL DIFFUSION  
A method of making a semiconductor device patterns a first fin in a pFET region, and patterns a second fin in an nFET region. A plurality of conformal microlayers containing a straining material...
US20120238074 METHODS AND APPARATUS FOR CONFORMAL DOPING  
Methods and apparatus for processing a substrate are provided herein. In some embodiments, a method of doping a substrate may include forming a dopant region on a substrate by implanting one or...
US20120037985 APPARATUS WITH CAPACITIVE COUPLING AND ASSOCIATED METHODS  
Transistors are described, along with methods and systems that include them. In one such transistor, a field plate is capacitively coupled between a first terminal and a second terminal. A...
US20120001253 FLATBAND VOLTAGE ADJUSTMENT IN A SEMICONDUCTOR DEVICE  
Memory devices, methods for fabricating, and methods for adjusting flatband voltages are disclosed. In one such memory device, a pair of source/drain regions are formed in a semiconductor. A...
US20110065262 Method of manufacturing semiconductor device  
A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming, on a surface of a semiconductor substrate, an isolation trench including...

Matches 1 - 32 out of 32