Matches 1 - 50 out of 107 1 2 3 >


Match Document Document Title
US20110165759 Tuning Capacitance to Enhance FET Stack Voltage Withstand  
An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string...
US20080237578 ULTRAHIGH DENSITY PATTERNING OF CONDUCTING MEDIA  
A nanoscale device and a method for creating and erasing of nanoscale conducting regions at the interface between two insulating oxides SrTiO3 and LaAlO3 is provided. The method uses the tip of a...
US20120043622 PROGRAMMABLE FETs USING Vt-SHIFT EFFECT AND METHODS OF MANUFACTURE  
Programmable field effect transistors (FETs) are provided using high-k dielectric metal gate Vt shift effect and methods of manufacturing the same. The method of controlling Vt shift in a high-k...
US20110163417 METHOD TO DYNAMICALLY TUNE PRECISION RESISTANCE  
A precision resistor is formed with a controllable resistance to compensate for variations that occur with temperature. An embodiment includes forming a resistive semiconductive element having a...
US20110089477 NANOSTRUCTURED MOS CAPACITOR  
The present invention provides nanostructured MOS capacitor that comprises a nanowire (2) at least partly enclosed by a dielectric layer (5) and a gate electrode (4) that encloses at least a...
US20100301321 Tunable Diode  
Tunable diodes and methods of making.
US20110217827 Removing Undesirable Nanotubes During Nanotube Device Fabrication  
Fabricating single-walled carbon nanotube transistor devices includes removing undesirable types of nanotubes. These undesirable types of nanotubes may include nonsemiconducting nanotubes,...
US20110081770 REMOVING UNDESIRABLE NANOTUBES DURING NANOTUBE DEVICE FABRICATION  
Fabricating single-walled carbon nanotube transistor devices includes removing undesirable types of nanotubes. These undesirable types of nanotubes may include nonsemiconducting nanotubes,...
US20110024716 MEMRISTOR HAVING A NANOSTRUCTURE IN THE SWITCHING MATERIAL  
A memristor includes a first electrode having a first surface, at least one electrically conductive nanostructure provided on the first surface, in which the at least one electrically conductive...
US20130122690 METHOD FOR REMOVING METALLIC NANOTUBE  
A method for removing a metallic nanotube which is formed on a substrate in a first direction is disclosed. The method may comprise: forming a plurality of conductors in a second direction...
US20080206964 Carbon Nanotube Transistor Process with Transferred Carbon Nanotubes  
During fabrication of single-walled carbon nanotube transistor devices, a porous template with numerous parallel pores is used to hold the single-walled carbon nanotubes. The porous template or...
US20130175499 Boundary-Modulated Nanoparticle Junctions And A Method For Manufacture Thereof  
A method of providing miniaturized size down to nanoscale electronic materials, which may be easily incorporated into the future ever-scaling down power electronics, microelectronics and...
US20120068269 Producing a perfect P-N junction  
This patent disclosure presents circuits, system, and method to produce an ideal memory cell and a method to produce a perfect PN junction without undesirable junction voltage and leakage current....
US20100308303 QUANTUM DOT MEMORY  
A method of making a quantum dot memory cell, the quantum dot memory cell including an array of quantum dots disposed between a first electrode and a second electrode, includes obtaining values...
US20120012901 Selective Functionalization by Joule Effect Thermal Activation  
The invention relates to a method for functionalizing a conductive or semiconductor material (M) by covalent grafting of receptor molecules (R) to its surface, said method comprising the following...
US20100314723 MANUFACTURING OF OPTICAL STRUCTURES BY ELECTROTHERMAL FOCUSSING  
This invention relates to methods and devices for the production of optical microstructures or domains in dielectric substrates based on electrothermal focussing. More specifically, the invention...
US20110306183 APPARATUS AND METHOD FOR MANUFACTURING POLYCRYSTALLINE SILICON THIN FILM  
An apparatus for manufacturing a polycrystalline silicon thin film, including a crystallization container filled with silicon oil, crystallization electrodes spaced apart from the crystallization...
US20150229165 RECTIFYING ANTENNA DEVICE WITH NANOSTRUCTURE DIODE  
A rectifying antenna device is disclosed. The device comprises a pair of electrode structures, and at least one nanostructure diode contacting at least a first electrode structure of the pair and...
US20110121258 RECTIFYING ANTENNA DEVICE WITH NANOSTRUCTURE DIODE  
A rectifying antenna device is disclosed. The device comprises a pair of electrode structures, and at least one nanostructure diode contacting at least a first electrode structure of the pair and...
US20150069618 Method for forming through wafer vias  
A method for forming through substrate vias (TSVs) in a non-conducting, glass substrate is disclosed. The method involves patterning a silicon template substrate with a plurality of lands and...
US20080316795 Method of making nonvolatile memory device containing carbon or nitrogen doped diode  
A method of making a nonvolatile memory device includes forming a first electrode, forming at least one nonvolatile memory cell comprising a silicon, germanium or silicon-germanium diode, doping...
US20140073113 PLASMA ETCHING METHOD AND PLASMA ETCHING APPARATUS  
A plasma etching method deposits a silicon-containing deposit by a plasma processing using a Si-containing gas on an object to be processed that includes a film to be processed, an organic film...
US20100197117 MIXED-SCALE ELECTRONIC INTERFACES  
Certain embodiments of the present invention are directed to a method of programming nanowire-to-conductive element electrical connections. The method comprises: providing a substrate including a...
US20100308302 Quantum Well Device  
An apparatus includes a primary planar quantum well and a planar distribution of dopant atoms. The primary planar quantum well is formed by a lower barrier layer, a central well layer on the lower...
US20090065803 Space-Charge-Free Semiconductor and Method  
A semiconductor having a an n-type material and a p-type material, wherein the n-type material and p-type material are joined to form a space-charge-free p-n junction. The energy of the...
US20110304023 METHOD OF GENERATING A HOLE OR RECESS OR WELL IN A SUBSTRATE  
The present invention relates to a method of generating a hole or recess or well in an electrically insulating or semiconducting substrate, and to a hole or recess or well in a substrate generated...
US20070218574 Semiconductor laser manufacturing method  
A method of manufacturing a semiconductor laser that has a ridge portion formed with a compound semiconductor layer containing Ga includes applying an electric current to the semiconductor laser...
US20110101309 GRAPHENE BASED SWITCHING DEVICE HAVING A TUNABLE BANDGAP  
A method of implementing bandgap tuning of a graphene-based switching device includes subjecting a bi-layer graphene to an electric field while simultaneously subjecting the bi-layer graphene to...
US20120138885 ELECTRICAL CIRCUIT COMPONENT  
An electrical circuit component includes a first electrode, a plurality of second electrodes and a negative differential resistance (NDR) material. The first electrode and the plurality of second...
US20140211346 Area-Efficient High Voltage Bipolar-Based ESD Protection Targeting Narrow Design Windows  
An area-efficient, high voltage, single polarity ESD protection device (300) is provided which includes an p-type substrate (303); a first p-well (308-1) formed in the substrate and sized to...
US20120052649 BISTABLE NANOSWITCH  
A non-volatile bistable nano-electromechanical switch is provided for use in memory devices and microprocessors. The switch employs carbon nanotubes as the actuation element. A method has been...
US20120168713 METHOD FOR MANUFACTURING A SILICON NANOWIRE ARRAY USING A POROUS METAL FILM  
The present invention is to provide a method for manufacturing a silicon nanowire array comprising (a) preparing a porous metal film; (b) placing the porous metal film in contact with a silicon...
US20120248568 METHOD FOR CONTROLLING THE ELECTRICAL CONDUCTION BETWEEN TWO METALLIC PORTIONS AND ASSOCIATED DEVICE  
A method for controlling the electrical conduction between two electrically conductive portions may include placing of an at least partially ionic crystal between the two electrically conductive...
US20140273403 LIGHT INDUCED NANOWIRE ASSEMBLY  
The invention provides a method for assembling semiconducting nanowires, which method can include providing a mixture comprising a dielectric solvent and two or more semiconducting nanowires,...
US20120256160 Piezo-phototronic Effect Devices  
A semiconducting device includes a piezoelectric structure that has a first end and an opposite second end. A first conductor is in electrical communication with the first end and a second...
US20110215289 ULTRAHIGH DENSITY PATTERNING OF CONDUCTING MEDIA  
A reconfigurable device and a method of creating, erasing, or reconfiguring the device are provided. At an interface between a first insulating layer and a second insulating layer, an electrically...
US20150072508 DIRECTIONAL SIO2 ETCH USING PLASMA PRE-TREATMENT AND HIGH-TEMPERATURE ETCHANT DEPOSITION  
Methods for processing a substrate are described herein. Methods can include positioning a substrate with an exposed surface comprising a silicon oxide layer in a processing chamber, biasing the...
US20130154109 METHOD OF LOWERING CAPACITANCES OF CONDUCTIVE APERTURES AND AN INTERPOSER CAPABLE OF BEING REVERSE BIASED TO ACHIEVE REDUCED CAPACITANCE  
The disclosure provides an interposer with conductive paths, a three-dimensional integrated circuit (3D IC), a method of reducing capacitance associated with conductive paths in an interposer and...
US20080224123 Methods for nanowire alignment and deposition  
The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e.g., an alternating current electric field) is used to align and associate nanowires with...
US20140011339 METHOD FOR REMOVING NATIVE OXIDE AND RESIDUE FROM A GERMANIUM OR III-V GROUP CONTAINING SURFACE  
Native oxides and residue are removed from surfaces of a substrate by performing a hydrogen remote plasma process on the substrate. In one embodiment, the method for removing native oxides from a...
US20140291606 SOLUTION-ASSISTED CARBON NANOTUBE PLACEMENT WITH GRAPHENE ELECTRODES  
A semiconductor device includes a substrate having at least one electrically insulating portion. A first graphene electrode is formed on a surface of the substrate such that the electrically...
US20060141751 Method for making a silicon dioxide layer on a silicon substrate by anodic oxidation  
A method for forming silicon dioxide layer on a silicon substrate by anodic oxidation includes: providing a silicon substrate which has a polished face; providing an anodic oxidation apparatus...
US20140299840 GRAPHENE LAMINATE WITH BAND GAP  
A graphene laminate includes a first piezoelectric material layer having a negatively-charged surface and a positively-charged surface, a first graphene layer under the first piezoelectric...
US20100055879 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE  
A wafer is mounted on the top surface of the stage having an electrostatic chuck function, and the wafer at 50° C. or more is cooled to a temperature lower than 50° C. In this step, the voltage to...
US20150084094 SCR COMPONENT WITH TEMPERATURE-STABLE CHARACTERISTICS  
An SCR-type component of vertical structure has a main upper electrode formed on a silicon region of a first conductivity type which is formed in a silicon layer of a second conductivity type. The...
US20120205719 DOUBLE GATED 4F2 DRAM CHC CELL AND METHODS OF FABRICATING THE SAME  
A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein the first gate is formed above the...
US20050037620 Method for achieving wafer contact for electro-processing  
A conductive type of seed or process film is used to cover the front side, the side, and at least a portion of the back side of a semiconductor wafer. The portion of the film which is on the back...
US20130203242 METHOD FOR MANUFACTURING A NANOWIRE STRUCTURE  
The present invention provides a method for aligning nanowires which can be used to fabricate devices comprising nanowires that has well-defined and controlled orientation independently on what...
US20130023070 PRODUCTION METHOD FOR OXIDIZED CARBON THIN FILM, AND ELEMENT HAVING OXIDIZED CARBON THIN FILM AND PRODUCTION METHOD THEREFOR  
The production method for the oxidized carbon thin film of the present disclosure includes: a first step of preparing a carbon thin film and iron oxide that is in contact with the carbon thin film...
US20100190319 METHOD OF FORMING MEMORY WITH FLOATING GATES INCLUDING SELF-ALIGNED METAL NANODOTS USING A COUPLING LAYER  
Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a...

Matches 1 - 50 out of 107 1 2 3 >