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US20150228589 INDEXING OF ELECTRONIC DEVICES WITH MULTIPLE WEIGHT MARKERS  
A die has a positional location in a wafer defined by first and second coordinates, the first and second coordinates identifying a respective horizontal and vertical location where the die was...
US20150221553 COOLED TAPE FRAME LIFT AND LOW CONTACT SHADOW RING FOR PLASMA HEAT ISOLATION  
Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a tape frame lift assembly for a plasma processing...
US20150221539 COOLED TAPE FRAME LIFT AND LOW CONTACT SHADOW RING FOR PLASMA HEAT ISOLATION  
Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a tape frame lift assembly for a plasma processing...
US20130075869 Chip Comprising a Fill Structure  
A chip includes a dielectric layer and a fill structure in the dielectric layer, wherein the fill structure extends along a dicing edge of the chip, with the fill structure abutting the dicing edge.
US20070176305 Alignment mark and overlay inspection mark  
An alignment mark is formed on an underlying layer and disposed on a region in which a semiconductor device is not formed. The alignment mark includes a plurality of strip-shaped patterns...
US20110039397 Structures and methods to separate microchips from a wafer  
Structures and methods for separating chips or ICs from a wafer are disclosed. To save area and manufacturing costs, deep trench formation combining with mechanical bending or lateral etch is used...
US20150194346 METHODS OF LOCALIZED HARDENING OF DICING CHANNEL  
Various embodiments include localized hardening of dicing channels in an integrated circuit (IC) wafer. In some embodiments, a method includes: applying localized heat to a metal interconnect in a...
US20140167225 Crack Stop Barrier and Method of Manufacturing Thereof  
A wafer is disclosed. The wafer comprises a plurality of chips and a plurality of kerfs. A kerf of the plurality of kerfs separates one chip from another chip. The kerf comprises a crack stop barrier.
US20120080673 Crack Stop Barrier and Method of Manufacturing Thereof  
A wafer is disclosed. The wafer comprises a plurality of chips and a plurality of kerfs. A kerf of the plurality of kerfs separates one chip from another chip. The kerf comprises a crack stop barrier.
US20140127882 WAFER PROCESSING METHOD  
A wafer processing method includes: a protective member providing step of providing a protective member on the front side of a wafer; a wafer quarter generating step of cutting the wafer along the...
US20130210215 PACKAGING METHOD WITH BACKSIDE WAFER DICING  
A packaging method with backside wafer dicing includes the steps of forming a support structure at the front surface of the wafer then depositing a metal layer on a centre area of the backside of...
US20150001683 DICE BEFORE GRIND WITH BACKSIDE METAL  
A method including forming a plurality of dicing channels in a front side of a wafer; the plurality of dicing channels including a depth at least greater than a desired final thickness of the...
US20120119385 Electrical Connector Between Die Pad and Z-Interconnect for Stacked Die Assemblies  
Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the...
US20090194850 Crack Stops for Semiconductor Devices  
Crack stops for semiconductor devices, semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a barrier structure for a semiconductor device...
US20110097875 WAFER PROCESSING METHOD  
A wafer processing method for dividing a wafer into individual devices along a plurality of crossing streets formed on the front side of the wafer, the individual devices being respectively formed...
US20140073067 WAFER PROCESSING METHOD  
A wafer processing method divides a wafer along a plurality of crossing streets formed on the front side of the wafer to thereby partition a plurality of regions where a plurality of devices are...
US20110114949 TEST CHIPLETS FOR DEVICES  
A method of forming a device is disclosed. The method includes providing a substrate on which the device is formed. It also includes forming a test cell on the substrate. The test cell includes a...
US20090057842 SELECTIVE REMOVAL OF ON-DIE REDISTRIBUTION INTERCONNECTS FROM SCRIBE-LINES  
Selective removal of on-die redistribution interconnect material from a scribe-line region is generally described. In one example, an apparatus includes a first semiconductor die having a...
US20130005116 EDGE-EXCLUSION SPALLING METHOD FOR IMPROVING SUBSTRATE REUSABILITY  
A method to minimize edge-related substrate breakage during spalling using an edge-exclusion region where the stressor layer is either non-present (excluded either during deposition or removed...
US20140141597 CHIPS WITH HIGH FRACTURE TOUGHNESS THROUGH A METAL RING  
A method of making an edge-reinforced microelectronic element is disclosed. The steps include mechanically cutting along dicing lanes of a substrate at least partially through a thickness thereof...
US20140077320 Scribe Lines in Wafers  
A wafer includes a plurality of chips arranged as rows and columns. A first plurality of scribe lines is between the rows of the plurality of chips. Each of the first plurality of scribe lines...
US20140127883 WAFER PROCESSING METHOD  
In a wafer processing method, a wafer is cut along a division line extending in a first direction through the center of the wafer and along a division line extending in a second direction through...
US20090077804 PRODUCTION LINE MODULE FOR FORMING MULTIPLE SIZED PHOTOVOLTAIC DEVICES  
The present invention generally relates to a sectioning module positioned within an automated solar cell device fabrication system. The solar cell device fabrication system is adapted to receive a...
US20120142165 Method of Avoiding Resin Outflow from the Wafer Scribe line in WLCSP  
A preparation process of wafer level chip scale packaging that prevents damaging a wafer in molding process is disclosed. In this process, a grinding grove is formed at a top side and around the...
US20050266661 Semiconductor wafer with ditched scribe street  
A semiconductor wafer (10) and associated methods are disclosed in which a plurality of semiconductor dice (14) include a semiconductor substrate (12) overlain by a plurality of upper layers (13)...
US20080194079 Method For Forming Median Crack In Substrate And Apparatus For Forming Median Crack In Substrate  
A method for forming a median crack and an apparatus for forming a median crack are provided, where the formation of a deep, straight median crack is possible, and an excellent broken surface of a...
US20070108638 ALIGNMENT MARK WITH IMPROVED RESISTANCE TO DICING INDUCED CRACKING AND DELAMINATION IN THE SCRIBE REGION  
A robust alignment mark used in semiconductor processing to help deter the expansion of cracks and delamination caused by the cutting of a dicing blade. A cross-shaped structure is used as a line...
US20100013059 DIFFUSION REGION ROUTING FOR NARROW SCRIBE-LINE DEVICES  
The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first...
US20140127884 WAFER PROCESSING METHOD  
In a wafer processing method, grooves are formed on the front side of a wafer along all division lines extending in a first direction and along all division lines extending in a second direction...
US20100203701 Crack Stop and Moisture Barrier  
A design for a crack stop and moisture barrier for a semiconductor device includes a plurality of discrete conductive features formed at the edge of an integrated circuit proximate a scribe line....
US20080042244 Nitride Compound Semiconductor Element and Production Method Therefor  
A nitride compound semiconductor element according to the present invention is a nitride compound semiconductor element including a substrate 1 having an upper face and a lower face and a...
US20070054471 ALIGNMENT MARK AND METHOD OF FORMING THE SAME  
An alignment mark is fabricated containing a mark portion and a trench structure. The trench structure surrounds the mark portion and is at a distance from the mark portion. The mark portion has a...
US20130299947 PASSIVATED TEST STRUCTURES TO ENABLE SAW SINGULATION OF WAFER  
A wafer having a die area and a scribe street is formed. The die area comprises die circuitry and a plurality of bond pads, and the scribe street comprises a test structure. Circuitry of the test...
US20110233705 WAFER PROCESSING  
Methods, devices, and systems for wafer processing are described herein. One method of wafer processing includes modifying a peripheral edge of a wafer to create a number of edge surfaces...
US20110147897 OFFSET FIELD GRID FOR EFFICIENT WAFER LAYOUT  
Techniques are provided for efficient wafer layout, which include the use of an offset grid to optimize use of available wafer space. As such, the number of identical die that can be fabricated on...
US20150024575 Wafer Alignment Methods in Die Sawing Process  
A method includes forming a molding compound molding a lower portion of an electrical connector of a wafer therein. The molding compound is at a front surface of the wafer. The molding compound...
US20120098104 SHIELDING TECHNIQUES FOR AN INTEGRATED CIRCUIT  
Described herein are techniques for forming, during wafer processing, a conductive shielding layer for a chip formed from a wafer. The conductive shielding layer can be formed on multiple sides of...
US20090137098 Method of manufacturing semiconductor element  
A step of forming a first auxiliary groove in a semiconductor element structure provided on a semiconductor substrate, a step of forming a second auxiliary groove in the semiconductor element...
US20090102071 Semiconductor substrate and method for manufacturing semiconductor device  
The present invention includes a first recognition mark which is arranged in a frame part of a perimeter of an implementation region having a plurality of semiconductor chips implemented therein...
US20140264767 Wafer, Integrated Circuit Chip and Method for Manufacturing an Integrated Circuit Chip  
A wafer has a number of IC areas and a kerf area arranged between the IC areas. The kerf area has a dicing area, a crack stop structure arranged between an IC area and a dicing area, and a trench...
US20150140784 WAFER PROCESSING METHOD  
A wafer processing method for dividing a wafer into individual devices along a plurality of crossing division lines, including a frame preparing step of preparing a frame having a plurality of...
US20100207251 Scribe Line Metal Structure  
A system and method for preventing defaults during singulation is presented. An embodiment comprises a dummy metal structure located in the scribe region. The dummy metal structure comprises a...
US20150099346 WAFER PROCESSING METHOD  
In a wafer processing method, the back side of the wafer is ground to reduce the thickness of the wafer to a predetermined thickness. A modified layer is formed by applying a laser beam to the...
US20090152683 ROUNDED DIE CONFIGURATION FOR STRESS MINIMIZATION AND ENHANCED THERMO-MECHANICAL RELIABILITY  
One aspect of the invention pertains to a semiconductor die with rounded sidewall junction edge corners. Such rounding reduces stress accumulations at those corners. In other embodiments of the...
US20090283760 Semiconductor device having principal surface of polar plane and side surface at specific angle to nonpolar plane and manufacturing method of the same  
A semiconductor device includes a substrate which is composed of a zinc oxide semiconductor having a hexagonal crystal structure and includes a first principal surface which is a polar plane; and...
US20130049195 Three-Dimensional Integrated Circuit (3DIC) Formation Process  
A method includes performing a laser grooving to remove a dielectric material in a wafer to form a trench, wherein the trench extends from a top surface of the wafer to stop at an intermediate...
US20090122822 Semiconductor device having trench extending perpendicularly to cleaved plane and manufacturing method of the same  
A method for manufacturing a semiconductor device includes setting cut lines in parallel to a normal direction of a (1-100) plane orthogonal to the principal plane and in parallel to a normal...
US20100155967 INTEGRATED CIRCUITS ON A WAFER AND METHOD OF PRODUCING INTEGRATED CIRCUITS  
Integrated circuits (Ia, Ib) on a wafer (2) comprise first and second integrated circuits (Ia, Ib) which each include an electric circuit (3). Only the first integrated circuits (Ia) comprise each...
US20120003817 INTEGRATED CIRCUIT WAFER DICING METHOD  
An integrated circuit wafer dicing method is provided. The method includes forming a plurality of integrated circuits and a plurality of test-keys on a wafer substrate, wherein the plurality of...
US20150200167 METHODS OF MANAGING METAL DENSITY IN DICING CHANNEL AND RELATED INTEGRATED CIRCUIT STRUCTURES  
Various embodiments include managing metal densities in kerf sections of an integrated circuit (IC) wafer. In some embodiments, a method includes: forming an integrated circuit (IC) wafer...