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US20130181355 Support Structure for TSV in MEMS Structure  
An embodiment is a method for forming a microelectromechanical system (MEMS) device. The method comprises forming a MEMS structure over a first substrate, wherein the MEMS structures comprises a...
US20150041827 BONDING STRUCTURE INCLUDING METAL NANO PARTICLES AND BONDING METHOD USING METAL NANO PARTICLES  
A bonding structure including metal nano particles includes a first member having a metal surface on at least one side, a second member having a metal surface on at least one side, the second...
US20110189834 SURFACE TREATMENT FOR MOLECULAR BONDING  
A method of bonding a first substrate to a second substrate by molecular bonding by forming an insulating layer on the bonding face of the first substrate, chemical-mechanical polishing of the...
US20120018855 METHOD OF PRODUCING A HETEROSTRUCTURE WITH LOCAL ADAPTATION OF THE THERMAL EXPANSION COEFFICIENT  
A method of producing a heterostructure by bonding at least one first substrate having a first thermal expansion coefficient onto a second substrate having a second thermal expansion coefficient,...
US20130341735 ANODICALLY BONDED STRAIN ISOLATOR  
A stress isolator that allows a sensor to be attached to materials of the same coefficient of thermal expansion and still provide the required elastic isolation between the sensor and the system...
US20120038027 METHOD FOR MOLECULAR ADHESION BONDING AT LOW PRESSURE  
The present invention relates to a method for molecular adhesion bonding between at least a first wafer and a second wafer involving aligning the first and second wafers, placing the first and...
US20120258579 DESIGN, LAYOUT, AND MANUFACTURING TECHNIQUES FOR MULTIVARIANT INTEGRATED CIRCUITS  
Techniques for the integral design, layout, and manufacture of integrated circuits include designing an integrated circuit that includes one variant having a plurality of a modular circuits...
US20120077329 DIRECT BONDING METHOD WITH REDUCTION IN OVERLAY MISALIGNMENT  
A method for the direct bonding of a first wafer having an intrinsic curvature before bonding to a second wafer having an intrinsic curvature before bonding, at least one of the two wafers...
US20120181661 METHOD FOR TUNING THE TRHESHOLD VOLTAGE OF A METAL GATE AND HIGH-K DEVICE  
A method of forming a deep trench capacitor includes providing a wafer. Devices are formed on a front side of the wafer. A through-silicon-via is formed on a substrate of the wafer. Deep trenches...
US20140235031 Methods for Wafer Bonding and for Nucleating Bonding Nanophases Using Wet and Steam Pressurization  
Substrates may be bonded according to a method comprising contacting a first bonding surface of a first substrate with a second bonding surface of a second substrate to form an assembly in the...
US20120126394 INTEGRATED CIRCUIT DEVICE AND METHOD FOR PREPARING THE SAME  
An integrated circuit device includes a bottom wafer, at least one stacking wafer positioned on the bottom wafer, and at least one conductive via penetrating through the stacking wafer and into...
US20150079759 Process for Bonding in an Atmosphere of a Gas Having a Negative Joule-Thomson Coefficient  
The present invention relates to a process for direct bonding two substrates, comprising at least: (a) bringing the surfaces to be bonded of said substrates in close contact; and (b) propagating a...
US20120299129 Process and Structure for High Temperature Selective Fusion Bonding  
A method to prevent movable structures within a MEMS device, and more specifically, in recesses having one or more dimension in the micrometer range or smaller (i.e., smaller than about 10...
US20150243629 Methods for Wafer Bonding, and for Nucleating Bonding Nanophases  
Substrates may be bonded according to a method comprising contacting a first bonding surface of a first substrate with a second bonding surface of a second substrate to form an assembly, and...
US20120132263 Methods for Wafer Bonding, and for Nucleating Bonding Nanophases  
Substrates may be bonded according to a method comprising contacting a first bonding surface of a first substrate with a second bonding surface of a second substrate to form an assembly; and...
US20140352787 DIRECT WAFER BONDING  
The disclosure provides for a direct wafer bonding method including providing a bonding layer upon a first and second wafer, and directly bonding the first and second wafers together under heat...
US20120138116 DIRECT WAFER BONDING  
The disclosure provides for a direct wafer bonding method including providing a bonding layer upon a first and second wafer, and directly bonding the first and second wafers together under heat...
US20050118787 System to form a layering of electronically-interactive material  
A machine controlled by a computer for depositing a liquefied electronically-interactive material on a sheet or support card, which includes: a base (1) to support the mobile bed (2) which is...
US20110014774 APPARATUS FOR TEMPORARY WAFER BONDING AND DEBONDING  
An improved apparatus for temporary wafer bonding includes a temporary bonder cluster and a debonder cluster. The temporary bonder cluster includes temporary bonder modules that perform electronic...
US20120074591 THIN WAFER SUPPORT ASSEMBLY  
A semiconductor wafer assembly formed by bonding a support wafer to a thin wafer using a double-sided bonding release tape. The support wafer provides support for the thin target wafer such that...
US20130316516 BONDING SYSTEM AND BONDING METHOD  
Disclosed is a bonding system which efficiently performs a bonding of a substrate to a support substrate, thereby improving the throughput in a bonding processing. The disclosed bonding system...
US20120112324 THROUGH-WAFER INTERCONNECTION  
A through-wafer interconnect and a method for fabricating the same are disclosed. The method starts with a conductive wafer to form a patterned trench by removing material of the conductive wafer....
US20070218589 Manufacturing method of multilayer wiring substrate  
A first multilayer wiring structural body 16 and a second multilayer wiring structural body 56 are simultaneously formed on both surfaces 101A, 101B of a substrate 101 and thereafter the portion...
US20120074417 Method of Bonding Wafers  
A method of bonding wafers with an aluminum-germanium bond includes forming an aluminum layer on a first wafer, and a germanium layer on a second wafer, and implanting the germanium layer with...
US20140042596 BONDED WAFER STRUCTURES  
The present disclosure includes bonded wafer structures and methods of forming bonded wafer structures. One example of a forming a bonded wafer structure includes providing a first wafer (202,...
US20120171809 Method and Apparatus for Forming a Thin Lamina  
A method for producing a lamina from a donor body includes implanting the donor body with an ion dosage and heating the donor body to an implant temperature during implanting. The donor body is...
US20120094435 METHOD OF FABRICATION OF AI/GE BONDING IN A WAFER PACKAGING ENVIRONMENT AND A PRODUCT PRODUCED THEREFROM  
A method of bonding of germanium to aluminum between two substrates to create a robust electrical and mechanical contact is disclosed. An aluminum-germanium bond has the following unique...
US20120168935 INTEGRATED CIRCUIT DEVICE AND METHOD FOR PREPARING THE SAME  
An integrated circuit device includes a bottom wafer having a first annular dielectric block, at least one stacking wafer having a second annular dielectric block positioned on the bottom wafer,...
US20150048509 CMOS COMPATIBLE WAFER BONDING LAYER AND PROCESS  
A wafer bonding layer and a process for using the same for bonding wafers are presented. The wafer bonding process includes providing a first wafer, providing a second type wafer and providing a...
US20070231972 Manufacture of programmable crossbar signal processor  
A process including a first step of providing a semiconductor wafer doped of a first conductivity type on a first side and doped of a second conductivity type, opposite to the first conductivity...
US20070020885 Tube Formed of Bonded Silicon Staves  
Tubular silicon members advantageously formed by extrusion from a silicon melt or by fixing together silicon staves in a barrel shape. A silicon-based wafer support tower is particularly useful...
US20060211218 Baffle wafers and randomly oriented polycrystalline silicon used therefor  
Baffle wafers of polycrystalline silicon are placed in non-production slots of a support tower for thermal processing monocrystalline silicon wafers. The polycrystalline silicon is preferably...
US20090206412 HYBRID ORIENTATION SCHEME FOR STANDARD ORTHOGONAL CIRCUITS  
Embodiments herein present device, method, etc. for a hybrid orientation scheme for standard orthogonal circuits. An integrated circuit of embodiments of the invention comprises a hybrid...
US20110129986 NITROGEN-PLASMA SURFACE TREATMENT IN A DIRECT BONDING METHOD  
Two plates, each comprising a thin layer of silicon or silicon oxide at a surface thereof, are bonded by subjecting the thin layer of at least one of the plates to a surface treatment step forming...
US20110143520 TWO-CHAMBER SYSTEM AND METHOD FOR SERIAL BONDING AND EXFOLIATION OF MULTIPLE WORKPIECES  
A system for treating distinct batches of workpieces to serial procedures comprises first and second multi-site structures. In each multi-site structure the sites are rotatable for alignment in...
US20090032970 STACKING OF INTEGRATED CIRCUITS USING GLASSY METAL BONDING  
Techniques associated with stacking integrated circuits using glassy metal bonding are generally described. In one example, an apparatus includes a first integrated circuit having one or more...
US20120015497 Preparing a Surface of a Sapphire Substrate for Fabricating Heterostructures  
A method of fabricating a heterostructure comprising at least a first substrate (120) made of sapphire and a second substrate (110) made of a material having a coefficient of thermal expansion...
US20110193197 STRUCTURE AND METHOD FOR MAKING CRACK STOP FOR 3D INTEGRATED CIRCUITS  
A structure to prevent propagation of a crack into the active region of a 3D integrated circuit, such as a crack initiated by a flaw at the periphery of a thinned substrate layer or a bonding...
US20130309840 COMBINATION OF A SUBSTRATE AND A WAFER  
The invention pertains to a combination of a substrate and a wafer, wherein the substrate and the wafer are arranged parallel to one another and bonded together with the aid of an adhesive layer...
US20130295746 COMBINATION OF A SUBSTRATE AND A WAFER  
The invention pertains to a combination of a substrate and a wafer, wherein the substrate and the wafer are arranged parallel to one another and bonded together with the aid of an adhesive layer...
US20060216908 Silicon parts joined by a silicon layer preferably plasma sprayed  
A method of joining two silicon members and the bonded assembly in which the members are assembled to place them into alignment across a seam. Silicon derived from silicon powder is plasma sprayed...
US20120025341 Aligning a sensor with a faceplate  
An assembly includes a first packaged device that contains a first image sensor having first fiducial marks thereon. On a portion of the first packaged device at a predetermined location relative...
US20060148129 Silicon direct bonding method  
A silicon direct bonding method including preparing two silicon substrates having corresponding bonding surfaces, forming a trench in at least one bonding surface of the two silicon substrates,...
US20070290369 Resin Paste For Die Bonding And Its Use  
Disclosed is a resin paste for die bonding comprising a butadiene homopolymer or copolymer (A) having a carboxylic acid terminal group, a thermosetting resin (B), a filler (C), and a printing...
US20140048805 BONDING-SUBSTRATE FABRICATION METHOD, BONDING SUBSTRATE, SUBSTRATE BONDING METHOD, BONDING-SUBSTRATE FABRICATION APPARATUS, AND SUBSTRATE ASSEMBLY  
[Problem] To provide a substrate bonding technique having a wide range of application. [Solution] A silicon thin film is formed on a bonding surface, and the interface with the substrate is...
US20100059762 HEAT REMOVAL FACILITATED WITH DIAMOND-LIKE CARBON LAYER IN SOI STRUCTURES  
Described are Silicon-on-Insulator devices containing a diamond-like carbon layer, methods of making the Silicon-on-Insulator devices, and methods of using the Silicon-on-Insulator devices.
US20140327113 3D INTEGRATED HETEROSTRUCTURES HAVING LOW-TEMPERATURE BONDED INTERFACES WITH HIGH BONDING ENERGY  
The invention relates to a process for assembling a first element that includes at least one first wafer, substrate or at least one chip, and a second element of at least one second wafer or...
US20140349465 JOINING DEVICE, JOINING SYSTEM AND JOINING METHOD  
A joining device for joining substrates with an intermolecular force includes a first holding unit configured to hold a first substrate on a lower surface thereof, a second holding unit installed...
US20070173032 Wafer dicing by channels and saw  
In a silicon wafer two channels are etched in each street separated enough to bracket the saw. The channels may be shallow. The saw blade is positioned within the two channels so that the outer...
US20130175698 Integrated Circuit Constructions Having Through Substrate Vias And Methods Of Forming Integrated Circuit Constructions Having Through Substrate Vias  
An integrated circuit construction includes a stack of two or more integrated circuit substrates. At least one of the substrates includes through substrate vias (TSVs) individually comprising...